OA Gear Fpga Class List

Here are the classes, structs, unions and interfaces with brief descriptions:

oagFpga::AiModGraph	Object for manipulating graphs in the module domain view
oagFpga::AiModRef	A reference into an and/inverter graph in a particular Module
oagFpga::FpgaMapper	A cut-based mapper
oagFpga::Manager	This class manages the functional description of a design
oagFpga::MapperUtils	A utility class for commonly used mapping-related functions
oagFpga::ModGraph	Object for manipulating graphs in the module domain view
oagFpga::ModRef	A reference into a Black Box graph in a particular Module
oagFpga::ModuleCompiler	Class for synthesizing various design objects into OpenAccess functional designs. AIG is used as the intermediate storage
oagFpga::MultiRef	A reference to a single-bit function, either an oaModBitNet* or an oagFpga::BBRef
oagFpga::Observer	A observer object to intercept save and open calls
oagFpga::OccGraph	Object for manipulating graphs in the occurrence domain view
oagFpga::OccRef	A reference into an and/inverter graph in a particular Occurrence object
oagFpga::RtlGraph	The intermediate data structure for storing the structural netlist with black boxes
oagFpga::RtlNode	The intermediate data structure for storing the structural netlist with black boxes
oagFpga::RtlNode::RtlMuxNodeInfo
oagFpga::RtlNode::RtlOptNodeInfo
oagFpga::RtlNode::RtlSeqNodeInfo
oagFpga::SimMod	An object for simulating input vectors on hierarchical designs
oagFunc::SimOcc	An object for simulating input vectors on hierarchical designs
oagFpga::Synthesis	Class for synthesizing various design objects into OpenAccess functional designs
oagFpga::Synthesis::Bounds
oagFpga::Synthesis::ConstantValue
oagFpga::VerilogDesign	An entire Verilog design
oagFpga::VerilogDesign::AlwaysBlock	An always block
oagFpga::VerilogDesign::Assignment	A continuous assignment
oagFpga::VerilogDesign::Bundle	A concatenation of expressions
oagFpga::VerilogDesign::Case	A single case inside of a case statement
oagFpga::VerilogDesign::Declaration	A wire, port, reg, or data type declaration
oagFpga::VerilogDesign::Expression	An expression
oagFpga::VerilogDesign::Function	A function definition
oagFpga::VerilogDesign::Instantiation	A module instantiation
oagFpga::VerilogDesign::Module	A single Verilog module
oagFpga::VerilogDesign::Port	A port definition (from inside a portlist)
oagFpga::VerilogDesign::PortConnection	A port connection inside of a module instantiation
oagFpga::VerilogDesign::Primary	An expression primary
oagFpga::VerilogDesign::Statement	A procedural statement
oagFpga::VerilogDesign::Trigger	A procedural trigger
oagFpga::VerilogSynthesis	Constructs OpenAccess objects and a functional description from a given VerilogDesign object
oagFpga::VerilogSynthesis::ConditionalLvalRef
oagFpga::VerilogSynthesis::FunctionVariableAssignment
oagFpga::VerilogSynthesis::LvalRef	This represents the destination of a left-hand assignment
oagFpga::VerilogSynthesis::ProceduralState
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