It is easier for us to debug if we can visualize the synthesized netlist in graph. My solution is to use Quartus as our visualization tool. Basically Quartus supports the black box in Verilog, which means that one can use a module without defining its implementation but just defining its input/output pins. The Verilog writer output all structural description (synthesized gate level netlist) as well as the black boxes used in the netlist, such as MUX_4, DFF_4, etc.
To download the Quartus tool, please go to Altera's download website and download the Quartus II Web Edition Software v7.1. You can need to finish the registeration procedures to activate the software.
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