Current Progress

Parts that have been accomplished

Finished the coding for the VPR-based synthesis flow.

Status of the system implementation (up to 07/09/07)

TODO list

class VerilogSynthesis

• Signed/Unsigned type is not recogized so far (see counters_7.v in XST benchmark). In fact, the Verilog parser/grammar needs to be updated since the following syntax is not supported yet.

  module v_counters_7 (C, CLR, Q);
      input C, CLR;
      output signed [3:0] Q;  // problemic coding 
      reg signed [3:0] tmp;   // problemic coding 
      ...
  endmodule
  

• Clock enable for a DFF is not recognized so far, alternatively, a MUX is inferred (see counters_5.v).

  //
  // 4-bit Unsigned Up Counter with Asynchronous Clear and Clock Enable
  //
  
  module v_counters_5 (C, CLR, CE, Q);
      input C, CLR, CE;
      output [3:0] Q;
      reg [3:0] tmp;
  
      always @(posedge C or posedge CLR)
      begin
          if (CLR)
              tmp <= 4'b0000;
          else if (CE)
              tmp <= tmp + 1'b1;
      end
  
      assign Q = tmp;
  
  endmodule
  

  

  Synthesized counters_5.v

• The zero expansion and the bit order for a BUS net connection is problemic (see counters_8.v).

• The clear/preset signal for a latch is NOT recognized, alternatively a MUX is inferred to implement the same functionality (see [latches_2.v] [latches_3.v]).

  //
  // 4-bit Latch with Inverted Gate and Asynchronous Preset
  //
  
  module v_latches_3 (G, D, PRE, Q);
      input G, PRE;
      input [3:0] D;
      output [3:0] Q;
      reg [3:0] Q;
  
      always @(G or D or PRE)
      begin
          if (PRE)
              Q = 4'b1111;
          else if (~G)
              Q = D;
      end
  endmodule
  

  

  Synthesized latches_3.v

• A comparator is not recoganized, alternatively a ">=" following a MUX is synthesized (see comparators_1.v).

  //
  // Unsigned 8-bit Greater or Equal Comparator
  //
  
  module v_comparator_1 (A, B, CMP);
      input  [7:0] A;
      input  [7:0] B;
      output CMP;
  
      assign CMP = (A >= B) ? 1'b1 : 1'b0;
  
  endmodule
  

  

  Synthesized comparators_1.v

• Arithmatic optimization for the case that divisor is 2^N, which should infer a bit shifter or shift bit directly if the divisor is a constant (see dividers*.v).

• RAM primitive is NOT inferred, instead multiple DFFs are inferred (see bram_map* and ram*).

• Shifter is not supported so far (see logical_shifters*.v)

• The following problems exist for handling MUXes: + [multiplexers_3.v] is not handled since a net ("o") is assigned multiple times. Tristate assignment should be considered.

  //
  // 4-to-1 1-bit MUX using tristate buffers.
  //
  
  module v_multiplexers_3 (a, b, c, d, s, o);
      input a,b,c,d;
      input [3:0] s;
      output o;
  
      assign o = s[3] ? a :1'bz;
      assign o = s[2] ? b :1'bz;
      assign o = s[1] ? c :1'bz;
      assign o = s[0] ? d :1'bz;
  endmodule
  

  + The "if-else if-else if-else" sequence should have be inferred as a MUX. [multiplexers_1.v]

  //
  // 4-to-1 1-bit MUX using an If statement.
  //
  
  module v_multiplexers_1 (a, b, c, d, s, o);
      input a,b,c,d;
      input [1:0] s;
      output o;
      reg o;
  
      always @(a or b or c or d or s)
      begin
          if (s == 2'b00) o = a;
          else if (s == 2'b01) o = b;
          else if (s == 2'b10) o = c;
          else o = d;
      end
  endmodule
  

  

  Synthesized (by BruinSyn) multiplexers_1.v

  + The synthesized logic for [multiplexers_4.v] is not as the same as the Quartus's result. Need to check the scenario with MUX and latches and the enable bit for a latch.

  //
  // 3-to-1 1-bit MUX with a 1-bit latch.
  //
  
  module v_multiplexers_4 (a, b, c, s, o);
      input a,b,c;
      input [1:0] s;
      output o;
      reg o;
  
      always @(a or b or c or s)
      begin
          if (s == 2'b00) o = a;
          else if (s == 2'b01) o = b;
          else if (s == 2'b10) o = c;
      end
  endmodule
  

  

  Synthesized (by BruinSyn) multiplexers_4.v

  

  Synthesized (by Quartus 7.1) multiplexers_4.v

• State machines are not recoginzed. (see state_machines_*.v)

class ModuleCompiler and FpgaMapper

• One potential problem to handle sequential devices is that I didn't differeciate latch and dff, which could cause functional error. One solution is to use a special naming label. I haven't fixed it at present since it should do not effect the technology mapping for the combinational portion of the circuit.
• The control signals of sequential devices (such as Latch and DFF) are not handled so far. Asynchronous signals such as clock, reset and preset don't need to be mapped but need to be extracted.

VerilogWriter

VerilogWriter needs to be updated as follows.

• the extra scalarNet due to the technology mapping
• the new instants due to mapped LUT
• double check "why no BB node was written in output.v", there should be an ADD BBnode

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