University of California Los Angeles
Design Automation Laboratory



Leakage Power Modeling and Reduction Considering Temperature and Process Variations

Primary Investigator (PI)

  • Prof. Lei He

Attended Students

  • Lerong Cheng
  • Fei Li
  • Weiping Liao
  • Yan Lin
  • Changbo Long
  • Phoebe Wang

Funding sources

Research Outcomes

    The leakage current in nanometer devices has increased drastically due to reduction in threshold voltage, channel length and gate oxide thickness, and most of the new devices under development also trade leakage for performance. In addition, an increasing number of modules in a highly integrated system are idle at any given time. The high-leakage devices and low-activity rates lead to significant leakage power at the system level, and leakage power has become a design concern with growing importance. Our contributions in the area include:

    System level leakage modeling and management. We developed leakage modeling and control considering data retention (ICCAD02, [1]). Applying VRC (Virtual Rail Clamping) to memory based units and considering power and delay extracted from detailed circuit design, we quantified the potential of leakage power reduction for typical workloads and each component in modern VLIW microprocessors, and showed that level-2 cache provides the largest gain of leakage power reduction. We compared a few mechanisms for online VRC scheduling and showed that time-out is simple but works best. Furthermore, we developed feedback control based time-out for largest power reduction with performance constraint and presented it in a paper accepted by TVLSI [2]. Finally, we also studied full-chip level interconnect power estimation with concurrent repeater and flip-flop insertion at ICCAD03 [3]. We showed that the structural information must be considered for accurate estimation, and doing so may reduce estimation error by 2.46x compared to previous work using purely stochastic interconnect distribution. We further quantified the need and performance and power impacts of interconnect pipelining.

    Supply voltage and temperature aware performance and power modeling. Both performance and leakage depend on supply voltage and temperature, but such dependency was not carefully modeled at the micro-architecture level. We first developed a register transfer level leakage estimation considering a rich cell library at ISPD01 [4] and an IEE journal paper [5], and then extended this method to accommodate temperature dependence in the context of microprocessors at ISLPED03 [6]. We finally incorporated such a model into micro-architecture simulation to close the loop between supply voltage, clock rate, power and temperature. We showed that ignoring inter-dependence between them may lead to thermal runaway (i.e., temperature goes to the infinity) or temperature violation in thermal management, and further quantified the benefits of advanced cooling techniques. The results were also presented as an invited paper at DAC04 [7] and will appear in TCAD [8].

    Distributed sleep transistor network. Sleep transistors are effective to reduce leakage power during standby modes. Previous work reduces the sleep transistor area by clustering gates to minimize the simultaneous switching current per cluster and then inserting a sleep transistor per cluster. We proposed a novel distributed sleep transistor network (DSTN), and showed that DSTN is intrinsically better than the cluster-based design in terms of the sleep transistor area and circuit performance. We revealed properties of optimal DSTN designs, and then developed an efficient algorithm for gate level DSTN synthesis. The algorithm obtains DSTN designs with up to 70.7% sleep transistor area reduction compared to cluster-based designs as verified by custom layout designs. DSTN was presented at DAC03 [9] and TVLSI [10] and it is employed by EDA tools under development at Cadence. In addition, we also presented how to place sleep transistors inside the power supply network at ISPD04 [11]. We proved that any valid placement leads to a same sleep transistor area if sleep transistors are sized optimally, which provides a large flexibility for sleep transistor placement.

    FPGA device and architecture evaluation considering process variation. Considering both die-to-die and within-die variations in effective channel length, threshold voltage, and gate oxide thickness, we developed closed-form models of leakage and timing variations at the FPGA chip level at ICCAD05[12]. Experiments show that our models are within 3% from Monte Carlo simulation, and the leakage and delay variations can be up to 3X and 1.9X, respectively. We then derive analytical yield models considering both leakage and timing variations, and use such models to evaluate FPGA device and architecture similar to a commercial FPGA and device setting from ITRS roadmap, device tuning alone improves leakage yield by 39% and architecture and device co-optimization increases leakage yield by 73%.


    [1]. W. Liao, J. Basile, and L. He, "Leakage Power Modeling and Reduction with Data Retention", IEEE/ACM ICCAD, 714-719, Nov. 2002. (pdf)

    [2]. Weiping Liao and Lei He, "Microarchitecture-level leakage Reduction with Data Retention", accepted by IEEE Transactions on Very Large Scale Integration Systems, 5 pages. (pdf).

    [3]. W. Liao and L. He, "Full-chip Interconnect Power Estimation and Simulation Considering Concurrent Repeater and Flip-flop Insertion," Proceedings of International Conference on Computer Aided Design, pages: 574-580, November 2003. (pdf)

    [4]. F. Li and L. He, "Maximum Current Estimation with Consideration of Power Gating," IEEE/ACM International Symposium on Physical Design, 106-111, April 2001. (pdf)

    [5]. Fei Li, Lei He, Joe Basile, Rakesh J. Patel and Hema Ramamurthy, "Leakage Current Aware High-Level Estimation for VLSI circuits", accepted by IEE Proceeding on Computers & Digital Techniques, special issue for 2003 International Workshop on Power and Timing Modeling, Optimization and Simulation. .

    [6]. W. Liao, F. Li and L. He, "Microarchitecture Level Power and Thermal Simulation Considering Temperature Dependent Leakage Model," in Proceedings of International Symposium on Low Power Electronics and Design, pages 211-216, August. 2003. (pdf)

    [7]. L. He, W. Liao and M. Stan, "System Level Leakage Reduction Considering Leakage and Thermal Interdependency", IEEE/ACM Design Automation Conference, pp. 12 - 17, June 2004. (pdf) (Invited paper)

    [8]. Weiping Liao, Lei He and Kevin Lepak, "Temperature and supply voltage aware performance and power modeling at microarchitecture level", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 12 pages, July 2005. (pdf).

    [9]. C. Long, and L. He, "Distributed Sleep Transistor Network for Leakage Power Reduction," IEEE/ACM Design Automation Conference, 181-186, June 2003. (pdf)

    [10]. Changbo Long and Lei He, "Distributed sleep transistor network for power reduction", IEEE Transactions on Very Large Scale Integration Systems, Pages 937-946, September, 2004 (pdf).

    [11]. C. Long, J. Xiong and L. He, "On Optimal Physical Synthesis of Sleep Transistors", International Symposium on Physical Design, pp. 156-161, April 2004. (pdf)

    [12]. P. Wong, L. Cheng, Y. Lin and L. He, "FPGA Device and Architecture Evaluation Considering Process Variation," Proc. IEEE/ACM International Conf. on Computer-Aided Design (ICCAD), San Jose, CA, Nov. 2005.

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Last update: 10-11-2002.