University of California Los Angeles
EDA Laboratory

Selected Publications

Books and Book Chapters

B1. J. Cong, L. He and C. K. Koh, "Layout Level Optimization For Low Power," a chapter in Low Power Design in Deep Submicron Electronics, edited by W. Nebel and J. Mermet, Kluwer Academic Publishers, 1997, pp. 205-265. 
B2. Z. Tang, N. Chang, S. Lin, W. Xie, S. Nakagawa, and L. He, ``Ramping Functional Units for Inductive Noise Reduction,'' a chapter in Springer Lecture Notes in Computer Science, Vol. 2008, Power Aware Computer Systems, edited by B. Falsafi and T. N. Vijaykumar, July 2001, pp. 13 -24 (pdf).
B3. L. He, ``Interconnect Modeling and Design with Consideration of On-Chip Inductance,'' a chapter in Layout Optimizations in VLSI Designs, edited by D. Z. Du and S. Sapatnekar, Kluwer Academic Publishers, Nov. 2001, pp. 155-190 (pdf).
B4. W. Liao and L. He, ``Power Modeling and Reduction of VLIW Processors,'' Compilers and Operating Systems for Low Power , edited by L. Benini, M. Kandemir and J. Ramanujam, ISBN: 1-4020-7573-1, Kluwer Academic Publishers, August 2003, Chapter 9, pp 155-172, (pdf).
B5. W. Liao and L. He, ``Coupled Power and Thermal Simulation with Active Cooling,'' Lecture Notes in Computer Science series, Springer-Verlag Publisher, Volume 3164/2004, pp 148-163, 2004. (pdf)
B6. Sheldon X.-D. Tan, and Lei He, ``Advanced Model Order Reduction Techniques for VLSI Designs,'' Cambridge University Press, pp 1-217, 2006.
B7. Shenghua Liu, Guoqiang Chen, Tom Tong Jing, Lei He, Robi Dutta, Xian-Long Hong, ''Diffusion-Driven Congestion Reduction for Substrate Topological Routing'', In Proc. of ISPD 2009, pp175-180, Mar. 2009. (ppt)

Journal Papers

J1. Y. Q. Zhang, L. He, J. R. Tong and P. S. Tang, "An Integrated CAD Software Development Environment,'' Chinese Journal of CAD and Graphics, vol. 5, No. 3, 1993. 
J2. L. He, J. R. Tong and P. S. Tang, "Development and Maintenance of CAD Software,'' Chinese Journal of CAD and Graphics, vol. 6, No. 1, 1994. 
J3. L. He, K. H. Zhang and P. S. Tang, "Fast Timing Simulation Considering Feedback Processing,'' Chinese Institute of Electronics- Journal of Electronics, April 1994. 
J4. L. He, K. H. Zhang and P. S. Tang, "FTSIM: A switch level fast timing simulator,'' Chinese Institute of Electronics- Acta Electronica Sinica, Feb. 1995, vol.23, (no.2):17-21. (Best Paper Award of Chinese CAD/CAM Conference, Oct. 1993). 
J5. J. Cong and L. He, "Optimal Wiresizing for Interconnects with Multiple Sources," ACM Transaction on Design Automation of Electronic Systems, Oct., 1996, pp. 478-511. (pdf).
J6. J. Cong, L. He, C.-K. Koh and P. H. Madden, "Performance Optimization of VLSI Interconnect Layout", invited survey, Integration, the VLSI Journal, vol. 21, 1996, pp. 1-94.  (pdf).
J7. J. Cong and L. He, "Theory and Algorithm of Local Refinement Based Optimization with Application to Device and Interconnect Sizing,"IEEE Tran. on Computer-Aided Design, April 1999, pp. 406-420 (pdf). (best paper nomination)
J8. J. Cong, L. He, C. K. Koh, and Z. Pan, ``Interconnect Sizing and Spacing Considering Coupling Capacitance,'' IEEE Trans. on Computer-Aided Design, vol. 20, no. 9, pp.1164-1169, Sep. 2001. (pdf).
J9. J. Xiong, L. He, "Full-chip Routing Optimization with RLC Crosstalk Budgeting", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, ,Volume: 23 , Issue: 3 , March 2004 Pages:366 - 377 (pdf).
J10. Ling Zhang, Tong Jing, Xianlong Hong, Jingyu Xu, Jinjun Xiong and Lei He, "CEE-Gr: A Global Router with Performance Optimization under Multi-Constraints", Chinese Journal of Semiconductors, 2004, 25(5), Pages: 508-515, (pdf).
J11. Kevin M. Lepak, Min Xu, Jun Chen and Lei He, "Simultaneous shield insertion and net ordering for capacitive and inductive coupling minimization", ACM Transactions on Design Automation of Electronic Systems, Volume 9, Issue 3, Pages: 290 - 309, 2004. (pdf).
J12. Changbo Long and Lei He, "Distributed sleep transistor network for power reduction", IEEE Transactions on Very Large Scale Integration Systems, Volume 12, Issue 9, September 2004, Pages 937-946 (pdf).
J13. Jinjun Xiong and Lei He, "Extended Global Routing with RLC Crosstalk Constraints", IEEE Transactions on Very Large Scale Integration Systems. Vol. 13, Issue 3, Pages 319-329, March 2005. (pdf).
J14. Jun Chen and Lei He, "Piece-wise linear model for transmission line with capacitive loading and ramp input", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 24, Issue 6, June 2005, Pages:928 - 937 (pdf).
J15. Weiping Liao, Lei He and Kevin Lepak, "Temperature and supply voltage aware performance and power modeling at microarchitecture level", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 24, Issue 7, July 2005, Pages: 1042 - 1053 (pdf).
J16. Jun Chen and Lei He, "Worst-Case Crosstalk Noise for Non-Switching Victims in High-speed Buses", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 24, Issue 8, Aug. 2005, Pages: 1275 - 1283 (pdf).
J17. Hao Yu and Lei He, "A Provably Passive and Cost Efficient Model for Inductive Interconnects", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 24, Issue 8, Aug. 2005, Pages:1283 - 1294 (pdf).
J18. Yan Lin, Fei Li and Lei He, "Circuits and Architectures for Field Programmable Gate Array with Configurable Supply Voltage", IEEE Transactions on Very Large Scale Integration Systems, Volume 13, Issue 9, Sept. 2005 Pages:1035 - 1047 (pdf).
J19. Fei Li, Lei He, Joe Basile, Rakesh J. Patel and Hema Ramamurthy, "Leakage Current Aware High-Level Estimation for VLSI circuits", IEEE Proceeding on Computers & Digital Techniques, special issue for 2003 International Workshop on Power and Timing Modeling, Optimization and Simulation, Volume 152, Issue 6, Nov. 2005, pages 747-755. (pdf).
J20. Fei Li, Yan Lin, Lei He, D. Chen, and J. Cong "Power Modeling and Characteristics of Field Programmable Gate Arrays", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 24, Issue 11, Nov. 2005, pages 1712-1724. (link).(the 3rd most downloaded paper in 2006 among all papers ever published by IEEE Trans. on CAD)
J21. Weiping Liao and Lei He, "Microarchitecture-level leakage Reduction with Data Retention", IEEE Transactions on Very Large Scale Integration Systems, Volume 13, Issue 11, pp. 1324-1328, November 2005. (pdf).
J22. Weiping Liao and Lei He, "Microarchitecture Level Interconnect Modeling Considering Layout Optimization," Journal of Low Power Electronics, Janurary 2006. (pdf)
J23. Z. Qi, H. Yu, P. Liu, S. Tan and L. He, "Wideband Passive Multi-Port Model Order Reduction and Realization of RLCM Circuits" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volumn 25, No 8, August 2006, pp 1496-1509. (pdf)
J24. J. Chen and L. He, "Modeling and Synthesis of Multi-Port Lossy Transmission Line for Multi-Channel Interconnect," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pages 1664-1676, Sept. 2006. (pdf)
J25. Y. Lin and L. He, "Dual-Vdd Interconnect with Chip-level Time Slack Allocation for FPGA Power Reduction," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 25, Issue 10, October 2006, pages: 2023 - 2034. (pdf)
J26. J. Xiong and L. He, "Full-Chip Multi-Level Routing for Power and Signal Integrity," Integration, the VLSI Journal, 40:226 - 234 (2007). (pdf)
J27. Lei He, Andrew Kahng, King Ho Tam, and Jinjun Xiong, "Simultaneous Buffer Insertion and Wire Sizing Considering Systematic CMP Variation and Random Leff Variation", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 26, No.4,Pages 78-85, May, 2007. (pdf)
J28. Fei Li, Yan Lin, and Lei He, "Field Programmability of Supply Voltages for FPGA Power Reduction", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol.26, No.4, Pages 752-764, April, 2007. (pdf)
J29. Jinjun Xiong, Vladimir Zolotov, Lei He, "Robust Extraction of Spatial Correlation," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol.26, No.4, Pages 2-9, April,2007. (pdf)
J30. Jun Chen, Lei He, "Efficient In-Package Decoupling Capacitor Optimization for I/O Power Integrity," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol.26, No.4, Pages 734-738, April, 2007. (pdf)
J31. Jinjun Xiong, and Lei He, "Probabilistic Transitive-closure Ordering and its Application on Variational Buffer insertion", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol.26, No.4, Pages 739-742, April, 2007. (pdf)
J32. Cheng, L., Li, F., Lin, Y., Wong, P. and He, L, "Device and Architecture Cooptimization for FPGA Power Reduction" Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Volume 26, Issue 7, July 2007 Page(s):1211 - 1221 (link)
J33. Liu P., Tan S. X.-D., McGaughy B., Wu L. and He L., "TermMerg: An Efficient Terminal Reduction Method for Interconnect Circuits" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol.26, No.8, Aug 2007 Page(s):1382 - 1392 (link)
J34. Changbo Long, Lucanus J. Simonson, Weiping Liao and Lei He, "Microarchitecture Configurations and Floorplanning Co-Optimization", IEEE Transactions on Very Large Scale Integration (VLSI)Systems, 15(7):830 - 841, July 2007. (pdf)
J35. Yan Lin, Mike Hutton and Lei He, "Statistical Placement for FPGAs considering process variation," IET Computers & Digital Techniques, Pages 267-275, vol. 1, 2007.
J36. Yiyu Shi, Paul Mesa, Hao Yu and Lei He, "Circuit Simulated Obstacle-Aware Steiner Routing," ACM Transactions on Design Automation of Electronic Systems, vol.1, Pages 1-18, 2007. (link)
J37. Zhen Cao, Tom Tong Jing, Jinjun Xiong, Yu Hu, Zhe Feng, Lei He and Xianlong Hong, "Fashion: A Fast and Accurate Solution to Global Routing Problem", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol.27, No.4, pp.726-737, April 2008.
J38. Yan Lin, Lei He and Mike Hutton, "Stochastic Physical Synthesis Considering Pre-routing Interconnect Uncertainty and Process Variation for FPGAs", IEEE Transactions on Very Large Scale Integration Systems Vol. 16, Feb 2008, Pages 124-133
J39. Yu Hu, Yan Lin, Lei He and Tim Tuan, "Physical Synthesis for FPGA Interconnect Power Reduction by Dual-Vdd Budgeting and Retiming", ACM Transactions on Design Automation of Electronic Systems (TODAES) Vol. 13 April 2008, Pages 30:1-30:29 (pdf)
J40. Xinyi Zhang, Lei He, Vassilios Gerousis, Li Song and Chin-Chi Ten, "Case Study and Efficient Modeling for Variational Chemical-Mechanical Planarization", accepted by IET Circuits, Devices & Systems
J41. Hao Yu, Yiyu Shi, Lei He and Tanay Karnik, "Thermal Via Allocation for 3D ICsConsidering Temporally and Spatially Variant Thermal Power", IEEE Transactions on VLSI Systems. Oct 2006, Pp:156-161 (pdf)
J42. Yiyu Shi, Jinjun Xiong, Chunchen Liu and Lei He, "Efficient Decoupling Capacitance Budgeting Considering Operationand Process Variations", accepted by IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
J43. King Ho Tam, Yu Hu, Lei He, Tom Tong Jing, and Xinyi Zhang, "Dual-Vdd Buffer Insertion for Power Reduction", IEEE Transactions on CAD of IC and Systems.VOL27, NO. 8 Aug. 2008, pp. 1498-1502 (pdf)
J44. Yu Hu, Victor Shih, Rupak Majumdar. and Lei He, "Exploiting Symmetries to Speed-Up SAT-Based Boolean Matching for Logic Synthesis of FPGAs", IEEE Transactions on CAD of Integrated Circuits and Systems, VOL 27, NO. 10, Oct 2008,pp1751-1760 (pdf)
J45. Yiyu Shi and Lei He, "EMPIRE: An Efficient and Compact Multiple-Parameterized Model Order Reduction Method for Physical Optimization", IEEE Transactions on VLSI Systems, 2007 Pages 51-58
J46. Lerong Cheng, Jinjun Xiong, Lei He, "Non-Gaussian Statistical Timing Analysis Using Second-Order Polynomial Fitting", IEEE Transactions on COMPUTER-AIDED DESIGN of IntegratedCircuits and Systems, 2008 Pages 298-303
J47. Shenghua Liu, Guoqiang Chen, Tom Tong Jing, Lei He, Tianpei Zhang, RobiDutta, and Xian-Long Hong, "Topological Routing to Maximize Routabilityfor Package Substrate", IEEE Transactions on CAD, Vol. 28, No.2, Feb2009, pp207-216.
J48. Yu Hu, Satyaki Das, Steve Trimberger and Lei He, "Design and Synthesis of Programmable Logic Block with Mixed LUT and Macro-Gate" IEEE Transactions on Computer-Aided Design for Circuit and Systems (TCAD) April 2009. Pages 591-595 (pdf)
J49. Hao Yu, Lei He, and M.C. Frank Chang, "Robust On-chip Signaling using Staggered and Twisted Interconnect", acceted by IEEE Design and Test of Computers (DTC),July 2009 (in press)
J50. Hao Yu, Joanna Ho and Lei He, "Allocating Power Ground Vias in 3D ICs for Simultaneous Power and Thermal Integrity" ACM Transactions on Design Automation of Electronic Systems (TODAES),May 2009 (in press). (pdf)
J51. Zhen Cao, Brian Foo, Lei He and Mihaela van der Schaar, "Optimality and Improvement of Dynamic Voltage Scaling Algorithms for Multimedia Applications" IEEE Transactions on Circuits and Systems I, 2008 Pages 179-184.
J52. Hao Yu, Chunta Chu, Yiyu Shi, David Smart,Lei He and Sheldon X.D. Tan, "Fast Analysis of Large Scale Inductive Interconnect by Block Structure Preserved Macromodeling" IEEE Transactions on Very large Scale Integration Systems(TVLSI) (in press)
J53. Lerong Cheng, Puneet Gupta, and Lei He, "Efficient Additive Statistical Leakage Estimation" IEEE Transactions on CAD(TCAD) (in press)
J54. Yiyu Shi, Jinjun Xiong, Howard Chen and Lei He, "Runtime Resonance Noise Reduction with Current Prediction Enabled Frequency Actuator" IEEE Transactions on Very large Scale Integration Systems(TVLSI) (in press)

Conference Papers

C1. L. He, K. H. Zhang and P. S. Tang, "An efficient feedback processing method for relaxation based fast timing simulation", IEEE International Symposium on VLSI Technology, Systems, and Applications, 12-14, May 1993.  (pdf).
C2. L. He, S. Chen, K. H. Zhang and P. S. Tang, "Implementation of Digital/Analog Mixed-Mode Simulation in SPICE", Int'l Conf. on Computer-Aided Design And Computer Graphics, pp. 577-81, vol.2, Aug. 1993. 
C3. L. He, K. H. Zhang and P. S. Tang, "A Switch-Level Fast-Timing Simulator", Int'l Conf. on Computer-Aided Design and Computer Graphics, pp. 565-70, vol.2, Aug. 1993. 
C4. J. Cong and L. He, "Optimal Wiresizing for Interconnects with Multiple Sources", ACM/IEEE Int'l Conf. on Computer-Aided Design, San Jose, CA, pp. 568-574, November 1995.  (pdf).
C5. J. Cong and L. He, "Simultaneous Transistor and Interconnect Sizing Based on the General Dominance Property", ACM SIGDA Workshop on Physical Design, Reston Sheraton, Virginia, pp. 34-39, April 1996.
C6. J. Cong and L. He, "An Efficient Approach to Simultaneous Transistor and Interconnect Sizing",ACM/IEEE Int'l Conf. on Computer-Aided Design, San Jose, CA, pp. 181-186, November 1996.  (pdf).
C7. J. Cong, L. He, A. B. Kahng, D. Noice, N. Shirali and S. H.-C. Yen, "Analysis and Justification of a Simple, Practical 2 1/2-D Capacitance Extraction Methodology", ACM/IEEE Design Automation Conference, June 1997, pp.627-632.  (pdf).
C8. J. Cong, L. He, K. Y. Khoo, C. K. Koh and Z. Pan, "Interconnect Design for Deep Submicron ICs", embedded tutorial, ACM/IEEE Int'l Conf. on Computer-Aided Design, San Jose, CA, November 1997, pp. 628-633 (ps).
C9. J. Cong and L. He, C. K. Koh and Z. Pan, "Global Interconnect Sizing and Spacing with Consideration of Coupling Capacitance", ACM/IEEE Int'l Conf. on Computer-Aided Design, San Jose, CA, November 1997, pp.478-485.  (pdf).
C10. J. Cong and L. He, "An Efficient Technique for Device and Interconnect Optimization in Deep Submicron Designs", ACM Int'l Symposium on Physical Design, pp. 45-51, Monterey, CA, April 1998.  (ps).
C11. L. He, N. Chang, S. Lin, and O. S. Nakagawa, "An Efficient Inductance Modeling for On-chip Interconnects", (nomination for Best Paper Award)IEEE Custom Integrated Circuits Conference, San Diego, CA, pp. 457-460, May 1999. (pdf).
C12. N. Chang, S. Lin, L. He, O. S. Nakagawa, and W. Xie, "Clocktree RLC extraction with Efficient Inductance Modeling", Design Automation and Test in Europe, pages: 522-526, Paris, France, March 2000  (pdf)
C13. L. He and K. M. Lepak, "Simultaneous shield insertion and net ordering for capacitive and inductive coupling minimization", IEEE/ACM International Symposium on Physical Design, pages: 55-60, San Diego, CA, April 2000 (pdf)
C14. L. He and Shen Lin, "Interconnect Modeling and Design for Gigascale Systems-on-Chip," invited tutorial, IEEE International ASIC/SOC Conference, Arlington, VA, September 2000. (pdf)
C15. Z. Tang, N. Chang, S. Lin, W. Xie, S. Nakagawa, and L He, "Ramp Up/Down Floating Point Unit to Reduce Inductive Noise," Workshop on Power-Aware Computer Systems, in conjuction with the Ninth International Conference on Architectural Support for Programming Languages and Operating Systems, pp.291-321, Nov., 2000. (pdf)
C16. L. Yin and L. He, "An Efficient Analytical Model for Coupled On-Chip RLC Interconnects," IEEE/ACM Asia South Pacific Design Automation Conference, pp. 385-390, Yokohama, Japan, January 2001. (pdf)
C17. Z. Tang, N. Chang, S. Lin, W. Xie, S. Nakagawa, and L. He, "Instruction prediction for step power reduction," IEEE International Symposium on Quality of Electronic Design, San Jose, CA, pp. 211-216, March 2001. (pdf)
C18. M. Xu and L. He, "An efficient model for frequency-based on-chip inductance," IEEE/ACM International Great Lakes Symposium on VLSI, West Lafayette, Indiana, pp. 115-120, March 2001. (pdf)
C19. J. D. Ma and L. He, "Simultaneous Signal and Power Routing Based on Keff Model,'' ACM International Workshop on System-Level Interconnect Prediction, Sonoma, CA, pp. 175-182, March 2001. (pdf)
C20. F. Li and L. He, "Maximum Current Estimation with Consideration of Power Gating," IEEE/ACM International Symposium on Physical Design, pp. 106-111, Sonoma County, CA, April 2001. (pdf)
C21. K. M. Lepak, I. Luwandi, and L. He, "Shield insertion and net ordering under explicit RLC noise constraint", Design Automation Conference, Las Vages, pp. 199-202, June 2001. (pdf)
C22. W. Liao and L. He, "Ongoing Work on Power Modeling and Reduction for VLIW Processors," Workshop on Compilers and Operating Systems for Low Power, Barcelona, Spain, pp. 100-108, September 2001. (pdf)
C23. J. D. Ma, A. Parihar, and L. He, "Pre-routing Estimation of Shielding for RLC Signal Integrity", International Conference on Computer Design, Austin, TX, September 2001. pp. 553-556 (pdf)
C24. J. D. Ma and L. He, "Formulae and Applications of Interconnect Estimation Considering Shielding Insertion and Net Ordering," IEEE/ACM International Conf. on Computer-Aided Design, San Jose, CA, November 2001. pp. 327-332 (pdf)
C25. F. Li, L. He, and K. K. Saluja, "Estimation of Maximum Power-up Current," Asia South Pacific Design Automation Conference, Japan, January 2002. pp. 51-56 (pdf)
C26. J. Chen,and L. He, "A Decoupling Method for Analysis of Coupled RLC Interconnects," in IEEE/ACM International Great Lakes Symposium on VLSI, New York, NY, April 2002. pp. 41 -46(pdf)
C27. J. D. Ma and L. He, "Toward Global Routing with RLC Crosstalk Constraints", IEEE/ACM Design Automation Conference, New Orleans, June 2002, pp. 669-672. (pdf)
C28. J. Xiong, J. Chen, and L. He, "Post Global Routing RLC Crosstalk Budgeting", IEEE/ACM ICCAD, pp. 504-509, San Jose, CA, Nov. 2002. (pdf)
C29. W. Liao, J. Basile, and L. He, "Leakage Power Modeling and Reduction with Data Retention", IEEE/ACM ICCAD, San Jose, CA, pp. 714-719, Nov. 2002. (pdf)
C30. J. Chen, L. He, "Determination of Worst-Case Crosstalk Noise for Non-Switching Victims in GHz+ Buses," ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, pp. 92-97, December, 2002. (pdf)
C31. J. Chen, L. He, "Determination of Worst-Case Crosstalk Noice for Non-Switching Victims in GHz+ Interconnects," IEEE/ACM Asia South Pacific Design Automation Conference, Japan, pp. 162-167, January 2003. (pdf)
C32. F. Li, D. Chen, L. He and J. Cong, "Architecture Evaluation for Power Efficient FPGAs", ACM International Symposium on Field Programmable Gate Array, Monterey, CA, pp. 175-184, February 2003. (pdf)
C33. H. Yu, and L. He, "Vector Potential Equivalent Circuit Based on PEEC Inversion," IEEE/ACM Design Automation Conference, Anaheim, CA, pp. 718-723, June 2003. (pdf) (ppt)
C34. C. Long, and L. He, "Distributed Sleep Transistor Network for Leakage Power Reduction," IEEE/ACM Design Automation Conference, Anaheim, CA, pp. 181-186, June 2003. (pdf)
C35. W. Liao, F. Li and L. He, "Microarchitecture Level Power and Thermal Simulation Considering Temperature Dependent Leakage Model," in Proceedings of International Symposium on Low Power Electronics and Design, Seoul, Korea, pages 211-216, August. 2003. (pdf)
C36. F. Li, L. He, J. Basile, R.Patel and H. Ramamurthy, "High-level Area and current estimation", 13th International Workshop on Power and Timing Modeling, Optimization and Simulation, Italy, pages: 259-268,September 2003. (pdf)
C37. L. Zhang, T. Jing, X. Hong, J. Xu, J. Xiong and L. He, "Performance optimization global routing with RLC crosstalk constraints", International Conference on ASIC, Beijing, China, Volume:1, 21-24, pp. 191-194, Oct. 2003. (pdf) (ppt) (Best Student Paper Award)
C38. W. Liao and L. He, "Full-chip Interconnect Power Estimation and Simulation Considering Concurrent Repeater and Flip-flop Insertion," Proceedings of International Conference on Computer Aided Design, San Jose, CA, pages: 574-580, November 2003. (pdf)
C39. W. Liao and L. He, "Coupled Power and Thermal Simulation and Its Application", in the 3rd Workshop on Power-Aware Computer Systems, in conjunction with the 36th Annual International Symposium on Microarchitecture, San Diego, CA, pp. 148-163, December 2003. (pdf)
C40. J. Chen and L. He, "Modeling and Synthesis of Coplanar Waveguide for Buffered Clock Tree", IEEE/ACM Asia South Pacific Design Automation Conference, Japan, pages: 367-372, January 2004. (pdf)
C41. F. Li, L. He, J. Basile, R. Patel and H. Ramamurthy, "High-level Area and Power-up current estimation considering Rich Cell Library", IEEE/ACM Asia South Pacific Design Automation Conference, Japan, pages: 899-904 January 2004. (pdf)
C42. J. Chen, L. He and S. Muddu, "Worst Case RLC Noise with Timing Window Constraints", ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Austin, TX, February, pages: 105-111, 2004. (pdf)
C43. J. Xiong and L. He, "Integrity-Driven Power and Signal Network Codesign", ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Austin, TX, pp. 119-126, February, 2004. (pdf)
C44. F. Li, Y. Lin, L. He and J. Cong, "Low-power FPGA using Dual-Vdd/Dual-Vt Techniques", the Twelfth International Symposium on Field Programmable Gate Arrays, pages: 42-50, Monterey, CA, February 2004. (pdf)
C45. D. Chen, J. Cong, F. Li and L. He,"Low Power Technology Mapping for FPGA Architectures with Dual Supply Voltages", the Twelfth International Symposium on Field Programmable Gate Arrays, Monterey, CA, pages: 109-117, February 2004. (pdf)
C46. J. Xiong and L. He, "Full-chip Multilevel Routing for Power and Signal Integrity", Design Automation and Test in Europe, Paris, France, pp. 1116-1121, March 2004. (pdf)
C47. L. Simonson, K. Tam, N. Akkiraju, M. Mohan and L. He, "Leveraging Delay Slack in Flip-flop and Buffer Insertion for Power Reduction", International Symposium on Quality Electronic Design, San Jose, CA, pages: 69-74, March 2004. (pdf)
C48. C. Long, J. Xiong and L. He, "On Optimal Physical Synthesis of Sleep Transistors", International Symposium on Physical Design, Phoenix, AZ, pp. 156-161, April 2004. (pdf)
C49. X. Zhao, Y. Cai, Q. Zhou, X. Long, L. He and J. Xiong, "Shielding area optimization under the solution of interconnect crosstalk" International Symposium on Circuits and Systems, Vancouver, Canada, Volume:5, 23-26, pp. 297-300, May 2004. (pdf)
C50. L. Zhang, T. Jing, X. Long, J. Xu, J. Xiong, L. He, "Performance and RLC Crosstalk Driven Global Routing", International Symposium on Circuits and Systems, Vancouver, Canada, Volume:5, 23-26, pp. 65-68, May 2004. (pdf) (ppt)
C51. C. Long, L. Simonson, W. Liao and L. He, "Floorplanning Optimization with Trajectory Piecewise-Linear Model for Pipelined Interconnects", IEEE/ACM Design Automation Conference, San Diego, CA, pp. 640-645, June 2004. (pdf)
C52. F. Li, Y. Lin and L. He, "FPGA Power Reduction Using Configurable Dual-Vdd", IEEE/ACM Design Automation Conference, pp. 735-740, San Diego, CA, June 2004. (pdf)
C53. L. He, W. Liao and M. Stan, "System Level Leakage Reduction Considering Leakage and Thermal Interdependency", IEEE/ACM Design Automation Conference, pp. 12 - 17, San Diego, CA, June 2004. (pdf) (Invited paper)
C54. H. Yu, L. He and S.X.D Tan, "Compact macro-modeling for on-chip RF passive components", Proc. IEEE International Conference on Communications, Circuits and Systems, 1195 - 1199, Vol. 2, June 2004. (pdf)
C55. L. He, A. B. Kahng., K. Tam and J. Xiong, "Variability-Driven Considerations in the Design of Integrated-Circuit Global Interconnects", IEEE VLSI Multilevel Interconnection Conference, pp. 214-221, Oct 2004. (pdf) (ppt) (Invited paper)
C56. F. Li, Y. Lin and L. He, "Vdd Programmability to Reduce FPGA Interconnect Power", IEEE/ACM International Conference on Computer-Aided Design, pp. 760-765, San Jose, CA, Nov. 2004. (pdf)
C57. J. Xiong and L. He, "Probabilistic Congestion Model Considering Shielding for Crosstalk Reduction", IEEE/ACM Asia and South Pacific Design Automation Conference, Shanghai, China, Jan. 2005, p739-742. (pdf)
C58. H.Yu, L. He and X. D. Tan, "A Wideband Realizable Circuit-Reduction for RLCM Interconnects", IEEE/ACM Asia and South Pacific Design Automation Conference, Shanghai, China, Jan. 2005, p111-114.(pdf)
C59. Y. Lin, F. Li and L. He, "Routing Track Duplication with Fine-Grained Power-Gating for FPGA Interconnect Power Reduction", IEEE/ACM Asia and South Pacific Design Automation Conference, Shanghai, China, Jan. 2005. p645-650(pdf) (ppt)
C60. Z. Qi, S. X.-D. Tan, H. Yu, L. He and P. Liu, "Wideband Modeling of RF/Analog Circuits via Hierarchical Multi-Point Model Order Reduction" IEEE/ACM Asia and South Pacific Design Automation Conference, Shanghai, China, Jan. 2005, p224-229.(pdf)
C61. T. Jing, L. Zhang, J. H. Liang, J. Xu, X. L. Hong, J. Xiong and L. He, "A min-area solution to performance and RLC crosstalk driven global routing problem", IEEE/ACM Asia and South Pacific Design Automation Conference, Shanghai, China, Jan. 2005, p115-120(pdf) (ppt)
C62. Y. Lin, F. Li and L. He, "Power modeling and architecture evaluation for FPGA with novel circuits for Vdd programmability", the Thirteenth International Symposium on Field Programmable Gate Arrays, pp. 199-207, Feb. 2005. (pdf) (ppt)
C63. L. He, A. B. Kahng, K. Tam and J. Xiong, "Design of IC Interconnects with Accurate Modeling of CMP", International Society for Optical Engineering (SPIE) Symposium on Microlithograhpy, pp. 109-119, March 2005. (pdf) (ppt)
C64. J. Xiong, K. Tam and L. He, "Buffer insertion considering process variation", Design Automation and Test in Europe, pp. 970-975, Munich, Germany, March 2005. (pdf)
C65. J. Wong, W. Liao, F. Li, L. He and M. Potkonjak, "Scheduling of Soft Real-Time Systems for Context-Aware Applications", Design Automation and Test in Europe, Munich, Germany, pp. 318-323, March 2005. (pdf)
C66. H. Yu and L. He, "Analysis and Synthesis of Staggered Twisted Bundle for Crosstalk Reduction", International Symposium on Quality Electric Design, pp. 682-687, March 2005. (pdf) (ppt)
C67. L. He, A. B. Kahng, K. Tam and J. Xiong, "Simultaneous Buffer Insertion and Wire Sizing Considering Systematic CMP Variation and Random Leff Variation", International Symposium on Physical Design, San Francisco, CA, pp.78-85, April 2005. (pdf) (ppt)
C68. H. Yu and L. He, "A Sparsified Vector Potential Equivalent Circuit Model for Massively Coupled Interconnects", International Symposium on Circuits and Systems, Kobe, Japan, May 2005. (pdf)
C69. K. Tam and L. He, "Power-Optimal Dual-Vdd Buffered Tree Considering Buffer Stations and Blockages", Design Automation Conference, Anaheim, CA, pp. 497-502, June 2005(pdf) (ppt)
C70. Y. Lin, and L. He, "Leakage efficient chip-level dual-vdd assignment with time slack allocation for FPGA power reduction", Design Automation Conference, Anaheim, CA, pp. 720-725, June 2005. (pdf) (ppt)
C71. L. Cheng, P. Wong, F. Li, Y. Lin and L. He, "Device and Architecture Co-Optimization for FPGA Power Reduction", Design Automation Conference, Anaheim, CA, pp. 915-920, June 2005. (pdf) (ppt)
C72. L. J. Simonson and L. He, "Micro-Architecture Performance Estimation by Formula", SAMOS V: Embedded Computer Systems: Architectures, Modeling, and Simulation, Samos, Greece, pp. 192-201, July 18-20, 2005 (pdf).
C73. Y. Chang, K. Tam and L. He, "Power-Optimal Repeater Insertion Considering Vdd and Vt as Design Freedoms", International Symposium on Low Power Electronics and Design, San Diego, CA, pp. 137-141, August 2005. (pdf)
C74. Hao Yu, Lei He, and Sheldon X.D. Tan "Block Structure Preserving Model Reduction for Linear Circuits with Large Numbers of Ports", IEEE International Behavioral Modeling and Simulation Conference, pp. 1-6, San Jose, CA, September 22-23, 2005. (pdf) (ppt)
C75. J. Chen and L. He, "Transmission Line Modeling and Synthesis for Multi-Channel Communication," IEEE International Behavioral Modeling and Simulation Conference, San Jose, CA, pp. 94-99, September 22-23, 2005. (pdf)
C76. Jinghong Liang, Tong Jing, Xianlong Hong, Jinjun Xiong, Lei He, "Power/Ground Network Aware and Row-Based Solutions to the Crosstalk Driven Routing Problem", In: Proceedings of IEEE ASICON, Shanghai, China, Oct, 2005, pp.776-779 (pdf) (ppt)
C77. P. Wong, L. Cheng, Y. Lin and L. He, "FPGA Device and Architecture Evaluation Considering Process Variation," Proc. IEEE/ACM International Conf. on Computer-Aided Design (ICCAD), San Jose, CA, pp. 19-24, Nov. 2005. (pdf)
C78. P. Liu, S. X.-D. Tan, H. Li, Z. Qi, J. Kong, B. McGaughy, L. He, "An efficient method for terminal reduction of interconnect circuits considering delay variations", Proc. IEEE/ACM International Conf. on Computer-Aided Design (ICCAD), San Jose, CA, pp. 821-826, Nov. 2005. (pdf)
C79. Yiyu Shi, Tong Jing, Lei He and Zhe Feng, "CDCTree: Novel Obstacle-Avoiding Routing Tree Construction based on Current Driven Circuit Model", Proc. IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), Japan, pp. 630-635, 2006. (pdf) (ppt)
C80. Jinjun Xiong, YC Wong, Egino Sarto, Lei He, "Constraint Driven I/O Planning and Placement for Chip-package Codesign", Proc. IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), Japan, pp. 207-212, 2006. (pdf) (ppt)
C81. Jinjun Xiong, Vladimir Zolotov, Lei He, "Robust Extraction of Spatial Correlation," IEEE/ACM International Symposium on Physical Design, San Jose, CA, pp. 2-9, April 2006. (Best Paper Award ).  (pdf) (ppt)
C82. Jinjun Xiong, Lei He, "Fast Buffer Insertion Considering Process Variations", IEEE/ACM International Symposium on Physical Design, San Jose, CA, pp. 128-135, April 2006. (pdf) (ppt)
C83. Yiyu Shi, Hao Yu and Lei He, "Generalized Second-Order Arnoldi Method for Model Order Reduction with Multiple Non-impulse Sources", IEEE/ACM International Symposium on Physical Design, San Jose, CA, pp. 25-32, April 2006. (pdf) (ppt)
C84. Jun Chen, Lei He, "Noise-Driven In-Package Decoupling Capacitance Insertion," IEEE/ACM International Symposium on Physical Design, San Jose, CA, pp. 94-101, April 2006. (pdf)
C85. Hao Yu, Yiyu Shi and Lei He, "Fast Analysis of Structured Power Grid by Triangularization Based Structure Preserving Model", in proceedings of IEEE/ACM Design Automation Conference, San Francisco, CA, pp. 205-210, July 2006. (nomination for Best Paper Award) (pdf) (ppt)
C86. Yiyu Shi, Paul Mesa, Hao Yu and Lei He, "Circuit Simulation Based Obstacle-aware Steiner Routing", in proceedings of IEEE/ACM Design Automation Conference, San Francisco, CA, pp. 385-388, July 2006. (pdf) (ppt)
C87. Yu Hu, Yan Lin, Lei He and Tim Tuan, "Simultaneous Time Slack Budgeting and Retiming for Dual-Vdd FPGA Power Reduction", in proceedings of IEEE/ACM Design Automation Conference, San Francisco, pp. 478-483, CA, July 2006. (pdf) (ppt)
C88. Yan Lin, Mike Hutton and Lei He, "Placement and Timing for FPGAs Considering Variations", International Conference on Field Programmable Logic and Applications, August 2006 (pdf) (ppt)
C89. Lerong Cheng, Jinjun Xiong, Lei He, "FPGA Performance Optimization via Chipwise Placement Considering Process Variations", International Conference on Field Programmable Logic and Applications, August 2006 (pdf)
C90. Hao Yu, Yiyu Shi, Lei He, and Tanay Karnik, "Thermal Via Allocation for 3D ICs Considering Temporally and Spatially Variant Thermal Power", International Symposium on Low Power Electronics and Design, October 2006. (pdf) (ppt)
C91. Yan Lin, Yu Hu and Lei He, "An Efficient Chip Level Time Slack Allocation Algorithm for Dual-Vdd FPGA Power Reduction", International Symposium on Low Power Electronics and Design, October 2006. (pdf) (ppt)
C92. Changbo Long, Sasank Reddy, Lei He, Sudhakar Pamarti, and Tanay Karnik, "Power-Efficient Pulse Width Modulation DC/DC Converters with Zero Voltage Switching Control", International Symposium on Low Power Electronics and Design, 326-329, Tegernsee, Germany, October 2006. (pdf)
C93. Hao Yu, Joanna Ho, and Lei He, "Simultaneous Power and Thermal Integrity Driven Via Stapling in 3D ICs", IEEE/ACM International Conf. on Computer-Aided Design (ICCAD), San Jose, CA, Nov. 2006. (nomination for Best Paper Award) (pdf) (ppt)
C94. Hao Yu, Yiyu Shi, and Lei He, "A First Order Block Structure Preserving Model Order Reduction with Inversed Inductance", IEEE/ACM International Conf. on Computer-Aided Design (ICCAD), San Jose, CA, Nov. 2006. (pdf) (ppt)
C95. Zhen Cao, Tong Jing, Jinjun Xiong, Yu Hu, Lei He, and Xianlong Hong, "DpRouter: A Fast and Accurate Dynamic-Pattern-Based Global Routing Algorithm", IEEE/ACM Asia and South Pacific Design Automation Conference(ASPDAC), Japan, Jan. 2007. pp.256-261 (pdf) (ppt)
C96. Yan Lin and Lei He, "Stochastic Physical Synthesis for FPGAs with Pre-routing Interconnect Uncertainty and Process Variation", IEEE/ACM International Symposium on Field-Programmable Gate Arrays, Monterey, California, 80-88, Feb 2007 (pdf) (ppt)
C97. Lerong Cheng, Jinjun Xiong, and Lei He, "Non-Linear Statistical Static Timing Analysis for Non-Gaussian Variation Sources", ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems(TAU), Austin, Texas, Feb. 2007. (pdf) (ppt)
C98. Yu Hu, King Ho Tam, Tom Tong Jing and Lei He, "Fast Dual-Vdd Buffering Based on Interconnect Prediction and Sampling", IEEE/ACM System Level Interconnect Prediction (SLIP), Austin, Texas, March, 2007. pp.95-102 (pdf) (ppt)
C99. Yiyu Shi and Lei He, "EMPIRE: An Efficient and Compact Multiple-Parameterized Model Order Reduction Method for Physical Optimizaion", International Symposium on Physical Design (ISPD), Austin, Texas, 51-58, March 2007. (pdf) (ppt)
C100. Hao Yu, Yu Hu, Chuenchen Liu, and Lei He, "Minimal Skew Clock Embedding Considering Time Variant Temperature Variation with Automatic Correlation Extraction", ACM International Symposium on Physical Design (ISPD), Austin, Texas, 173-180, March 2007. (pdf) (ppt)
C101. Yan Lin and Lei He "Statistical Dual-Vdd Assignment for FPGA Interconnect Power Reduction ", IEEE/ACM Design Automation and Test in Europe, 636-641, April 2007 (pdf)
C102. Yu Hu, Victor Shih, Rupak Majumdar and Lei He, "Exploiting Symmetry in SAT-Based Boolean Matching for Heterogeneous FPGA Technology Mapping ", IWLS, 2007. (pdf) (ppt)
C103. Yu Hu, Satyaki Das and Lei He, "Design, Synthesis and Evaluation of Heterogeneous FPGA with Mixed LUTs and Macro-Gates ", IWLS, 2007. (pdf) (ppt)
C104. Hao Yu, Chunta Chu and Lei He "Off-chip Decoupling Capacitor Allocation for Chip Package Co-Design", in Proceedings of IEEE/ACM Design Automation Conference, San Diego, California, 618-621, June 2007. (pdf) (ppt)
C105. Lerong Cheng, Jinjun Xiong and Lei He "Non-Linear Statistical Static Timing Analysis for Non-Gaussian Variation Sources", in Proceedings of IEEE/ACM Design Automation Conference, San Diego, California, 250-255, June 2007.
C106. Hao Yu, Yu Hu, Chun-Chen Liu and Lei He, Minimal Skew Clock Synthesis Considering Time Variant Temperature Gradient. SRC Techcon Conference, 2007. (pdf) (ppt)
C107. Yiyu Shi and Lei He, "EMPIRE: An Efficient and Compact Multiple-Parameterized Model Order Reduction Method for Physical Optimizaion", SRC Techcon Conference, 2007. (pdf) (ppt)
C108. Yiyu Shi, Jinjun Xiong, Chunchen Liu and Lei He, "Efficient Decoupling Capacitance Budgeting Considering Current Correlation Including Process Variation", IEEE/ACM International Conf. on Computer-Aided Design (ICCAD), San Jose, CA, Nov. 2007. (nomination for Best Paper Award) (pdf) (ppt)
C109. Yu Hu, Victor Shih, Rupak Majumdar and Lei He, "Exploiting Symmetry in SAT-Based Boolean Matching for Heterogeneous FPGA Technology Mapping", IEEE/ACM International Conf. on Computer-Aided Design (ICCAD), San Jose, CA, Nov. 2007. (pdf) (ppt)
C110. Yu Hu, Satyaki Das, Steve Trimberger and Lei He, "Design, Synthesis and Evaluation of Heterogeneous FPGA with Mixed LUTs and Macro-Gates", IEEE/ACM International Conf. on Computer-Aided Design (ICCAD), San Jose, CA, Nov. 2007. (pdf) (ppt)
C111. Yan Lin and Lei He, "Device and Architecture Concurrent Optimization for FPGA Transient Soft Error Rate", IEEE/ACM International Conf. on Computer-Aided Design (ICCAD), San Jose, CA, Nov. 2007. (pdf) (ppt)
C112. Chun-Ta Chu, Xinyi Zhang, Lei He and Tom Tong Jing, "Temperature Aware Microprocessor Floorplanning Considering Application Dependent Power Load", IEEE/ACM International Conf. on Computer-Aided Design (ICCAD), San Jose, CA, Nov. 2007. (pdf) (ppt)
C113. Lerong Cheng, Jinjun Xiong, and Lei He, "Non-Gaussian Statistical Timing Analysis Using Second-Order Polynomial Fitting", Proc. Asia South Pacific Design Automation Conf., 2008. (pdf) (ppt)
C114. Lerong Cheng, Yan Lin, Lei He, and Yu Cao, "TraceBased Framework for Concurrent Development of Process and FPGA Architecture Considering Process Variation and Reliability", Proc. ACM Intl. Symp. Field-Programmable Gate Arrays, 2008. (pdf) (ppt)
C115. Zhen Cao, Brian Foo, Lei He, and Mihaela van der Schaar , "Optimality and Improvement of Dynamic Voltage Scaling Algorithms for Multimedia Applications", accepted by IEEE/ACM Design Automation Conference, June, 2008, Anaheim, CA. (nomination for Best Paper Award)
C116. Yu Hu, Victor Shih, Rupak Majumdar, and Lei He, "FPGA Area Reduction by Multi-Output Function Based Sequential Resynthesis", accepted by IEEE/ACM Design Automation Conference, June, 2008, Anaheim, CA. (pdf) (ppt)
C117. Shenghua Liu, Guoqiang Chen, Tom Tong Jing, Lei He, Tianpei Zhang, Robi Dutta, and Xian-Long Hong, "Topological Routing to Maximize Routability for Package Substrate", In Proc. of 45th DAC, Anaheim, June 2008, pp.566-569. (ppt)
C118. Yu Hu, Zhe Feng, Rupak Majumdar, and Lei He, "Templates and Algorithms of Boolean Matching for Fault Tolerance in FPGAs", accepted by IWLS 2008.
C119. Yu Hu, Victor Shih, Rupak Majumdar, and Lei He, "FPGA Area Reduction by Multi-Output Function Based Sequential Resynthesis", accepted by IWLS 2008.
C120. Yu Hu, Zhe Feng, Lei He, and Ruapk Majumdar, "Robust FPGA Resynthesis Based on Fault Tolerant Boolean Matching", by ICCAD 2008. (nomination for Best Paper Award) (pdf) (ppt)
C121. Yiyu Shi, Lei He, and C.-J. Richard Shi, "Scalable Symbolic Model Order Reduction", IEEE Behaviorial Modeling and Simulation Conference 2008. (pdf) (ppt)
C122. Lerong Cheng, Puneet Gupta, and Lei He, "Accounting for Non-linear Dependence Using Function Driven Component Analysis", ASPDAC 2009. (pdf)
C123. Yiyu Shi, Wei Yao, Jinjun Xiong, and Lei He, "Incremental and On-demand Random Walk for Iterative Power Distribution Network Analysis", ASPDAC 2009. (pdf) (ppt)
C124. Yiyu Shi, Jinjun Xiong, Howard Chen, and Lei He, "Stochastic Current Prediction Enabled Frequency Actuator for Runtime Resonance Noise Reduction", (nomination for Best Paper Award) ASPDAC 2009. (pdf) (ppt)
C125. Ju-Yueh Lee, Yu Hu, Rupak Majumdar, Lei He, and Minming Li, "Fault-Tolerant Resynthesis for Dual-Output LUTs", SELSE, 2009.
C126. Shenghua Liu, Guoqiang Chen, Tom Tong Jing, Lei He, Robi Dutta and Xian-Long Hong, "Diffusion-Driven Congestion Reduction for Substrate Topological Routing", ISPD, 2009.
C127. Wei Yao, Yiyu Shi, Lei He and Sudhakar Parmati, "Worst Case Timing Jitter and Amplitude Noise in Differential Signaling", ISQED 2009.
C128. Ju-Yueh Lee, Yu Hu, Rupak Majumdar, and Lei He, "Simultaneous Test Pattern Compaction, Ordering and X-Filling for Testing Power Reduction", ISQED, 2009 (pdf) (ppt)
C129. Hao Yu and Lei He, "Dynamic Power and Thermal Integrity in 3D Integration" IEEE International Conference on Communications, Circuits and Systems, July 23-25, San Jose, USA. (invited paper) (pdf)
C130. Fang Gong, Hao Yu, and Lei He, "PiCAP: A Parallel and Incrementel Capacitance Extraction Considering Stochastic Process Variation", DAC 2009 (ppt)
C131. Lerong Cheng, Puneet, Costas Spanos, Kun Qian, and Lei He, "Physically Justiable Die-Level Modeling of Spatial Variation in View of Systematic Across Wafer Variability", DAC 2009
C132. Yu Hu, Lei He, "Power-Efficient and Fault-Tolerant Circuits and Systems", IEEE international Conference on Application Specific Integrated Circuits, Oct 2009, Changsha, China (invited paper).
C133. Wei Yao, Yiyu Shi, Lei He and Sudhakar Parmati, "Joint Design-Time and Post-Silicon Optimization for Digitally Tuned Analog Circuits", ICCAD 2009
C134. Zhe Feng, Yu Hu, Lei He and Rupak Majumdar, "IPR: In-Place Reconfiguration for FPGA Fault Tolerance", ICCAD 2009
C135. Wei Yao, Yiyu Shi and Lei He and Sudhakar Pamarti, "Worst Case Timing Jitter and Amplitude Noise in Di erential Signaling", SRC Techcon Conference, Texas, 2009
C136. Yiyu Shi, Wei Yao, Lei He and Sudhakar Pamarti, "Joint Design-time and Post-silicon Optimization for Analog Circuits: A Case Study Using A High-speed Transmitter", SRC Techcon Conference, Texas, 2009

Technical Reports

R1. L. He and M. Xu, "Modeling and Layout Optimization for On-chip Inductive Coupling," ECE Report 2000-01 (ps) (pdf)
R2. L. He and J. Xiong, "Full-chip Routing Optimization with RLC Crosstalk Budgeting," EE Report 2002-03 (pdf)
R3. L. He and H. Yu, "Vector Potential Equivalent Circuit Based on PEEC Inversion," EE Report 2002-03 (pdf)
R4. W. Liao and L. He, "System Level Leakage Reduction Considering the Interdependence of Temperature and Leakage," UCLA Engr. 04-249 (pdf)
R5. W. Liao, L. He and Kevin Lepak, "Temperature-Aware Performance and Power Modeling," UCLA Engr. 04-250 (pdf)

Tutorials

T1. J. Cong, L. He, K. Y. Khoo, C. K. Koh and Z. Pan, "Interconnect Design for Deep Submicron ICs", embedded tutorial, IEEE/ACM International Conference on Computer-Aided Design, November 1997.
T2. L. He and S. Lin, "Interconnect Modeling and Design for Gigascale Systems-on-Chip with Consideration of Inductance," half-day tutorial, IEEE International ASIC/SOC Conference, September 2000. (1, 2)
T3. L. He and S. Lin, "Signal Integrity for High-Performance Low-Power Circuits", half-day tutorial, IEEE International Symposium on Circuits and Systems, May 2002.
T4. H. Chen, E. Chiprout, and L. He, "Power, Timing and Signal Integrity in SoC Designs", half-day tutorial, IEEE/ACM Asia South-Pacific Design Automation Conference, January 2003. (1, 2, 3, 4 )
T5. L. Daniel, L. He, and B. Krauter, "Package-Chip Co-Design: Strategies and Challenges," half-day tutorial, IEEE/ACM International Symposium on Quality Electronic Design, March 2005. ( 1, 2, 3, 4 )
T6. L. He, M. Hutton, T. Tuan and S. Wilton, "Challenges and Opportunities for Low Power FPGAs in Nanometer Technologies," embedded tutorial, IEEE/ACM International Symposium on Low Power Electronics and Design, Aug. 2005. ( Introduction, 1, 2, 3, 4 )
T7. A. Devgan, S. Elassaad and L. He, "Design and Analysis at the Chip-Package Interface," half-day tutorial, IEEE/ACM International Conference on Computer-Aided Design, Nov. 2005.
T8. Paul M. Harvey, Howard Chen, Chung-Kuan Cheng, Manjid Borah, Lei He, and Sheldon Tan, "High Performance Interconnect and Packaging", full day tutorial, IEEE/ACM Asia South-Pacific Design Automation Conference, January 2006.
T9. Paul M. Harvey, Howard Chen, Lei He, Chung-Kuan Cheng, and Kaushik Sheth, "Surviving and Thriving in the World of Chip and Package Co-Design", full day tutorial, IEEE/ACM Design Automation Conference, July 2006.
T10. Silvakumar P. Mudanai, Noel Menezes, and Lei He, "Transistor, Cell, and Interconnect Modeling: Basics to Advances", half day tutorial, IEEE/ACM International Conference on Computer-Aided Design, 2006.

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Last update: 01-26-2007