Design Automation Laboratory







Released Tools

WArPE : Wisconsin Architecture Power Estimator

  • Input power density numbers from user or generate them from analytical models
  • Estimates average power consumed based on the choice of energy models for each unit
  • Inbuilt thermal model
  • Available online

TRIO2:interconnect synthesis under RLC model

  • RC and RLC interconnect extraction and analysis
  • RC and RLC SPICE netlist generation
  • Net ordering and shield insertion (SINO), spacing, and signal and power nets co-design (SPR), all under RLC model
  • Demonstrated at DAC'01 University Booth

iSIS: current and power estimation integrated with SIS package

PowerImpact: cycle-accurate performance and power simulator for VLIW processors

PTscalar: cycle-accurate performance and power simulator for SuperScalar processors

  • Based on SimpleScalar toolset for microarchitecture-level performance, power and thermal simulation
  • Consider interdependence between leakage power and temperature
  • Available online


cktSteiner: circuit simulation based obstacle-aware Steiner routing package

Spatial Detect: A matlab script to extract across-wafer variation from measurement data

ptrace2:trace-based FPGA power, delay, and reliability evaluation framework.


Laboratory: 53-109 Engineering IV, Telephone: (310)267-4950

Laboratory Director: Prof. Lei He , Boelter Hall 6731D

Email:, Telephone: (310)825-8282 ,Fax: (310)206-4685 ,Email :