• WArPE 1.0

• TRIO2

• iSIS

• PowerImpact

• fpgaEVA-LP2

• cktSteiner

• ptrace2

• SpatialDetect

Released Tools

WArPE : Wisconsin Architecture Power Estimator

• Input power density numbers from user or generate them from analytical models
• Estimates average power consumed based on the choice of energy models for each unit
• Inbuilt thermal model
• Available online

TRIO2:interconnect synthesis under RLC model

• RC and RLC interconnect extraction and analysis
• RC and RLC SPICE netlist generation
• Net ordering and shield insertion (SINO), spacing, and signal and power nets co-design (SPR), all under RLC model
• Demonstrated at DAC'01 University Booth

iSIS: current and power estimation integrated with SIS package

• Estimation of average current, maximum switching current and power-up current
• Available online

PowerImpact: cycle-accurate performance and power simulator for VLIW processors

• Based on IMPACT toolset for compiler optimization and microarchitecture-level performance simulation
• Integrating two parameterized power models
• Available online

PTscalar: cycle-accurate performance and power simulator for SuperScalar processors

Based on SimpleScalar toolset for microarchitecture-level performance, power and thermal simulation
• Consider interdependence between leakage power and temperature
• Available online

fpgaEVA-LP2:

• A power evaluation framework for Field Programmable Gate Arrays(FGPAs)
• Use VPR-LP based on VPR to obtain placement and routing result and generate BC-netlist back-annotated with post-layout capacitances and delays
• Use Psim to perform cycle-accurate simulation and obtain FPGA power consumption
• Available online

cktSteiner: circuit simulation based obstacle-aware Steiner routing package

• Map the uniform routing graph into an RC mesh
• Read in the pin locatons for a single net and reports the wirelength and runtime information
• Available online

Spatial Detect: A matlab script to extract across-wafer variation from measurement data

• Available online

ptrace2:trace-based FPGA power, delay, and reliability evaluation framework.

• Available online