oagFpga::VerilogSynthesis::ProceduralState Class Reference

#include <oagFpgaVerilogSynthesis.h>

Collaboration diagram for oagFpga::VerilogSynthesis::ProceduralState:

[legend]List of all members.

Public Types
enum	PStateType { PSTATE_SYNC, PSTATE_ASYNC }
Public Member Functions
	ProceduralState ()
Public Attributes
set< oa::oaModBitNet * >	dependencies
map< oa::oaModBitNet *, MultiRef >	blockingAssignments
map< oa::oaModBitNet *, MultiRef >	nonblockingAssignments
bool	isRegister
bool	isFunction
map< string, FunctionVariableAssignment >	functionAssignments
set< oa::oaModBitNet * >	normalTriggers
set< oa::oaModBitNet * >	posTriggers
set< oa::oaModBitNet * >	negTriggers
set< oa::oaModBitNet * >	nonClockTriggers
PStateType	pStateType
MultiRef	curTrigger
map< oa::oaModBitNet *, MultiRef >	aData
map< oa::oaModBitNet *, MultiRef >	aLoad

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Detailed Description

This data structure holds information about the state of variables within a procedural section of code.

Definition at line 59 of file oagFpgaVerilogSynthesis.h.

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Member Enumeration Documentation

enum oagFpga::VerilogSynthesis::ProceduralState::PStateType

Enumeration values: PSTATE_SYNC  PSTATE_ASYNC  Definition at line 76 of file oagFpgaVerilogSynthesis.h.

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Constructor & Destructor Documentation

oagFpga::VerilogSynthesis::ProceduralState::ProceduralState (   )  [inline]

Definition at line 88 of file oagFpgaVerilogSynthesis.h.

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Member Data Documentation

map<oa::oaModBitNet*, MultiRef> oagFpga::VerilogSynthesis::ProceduralState::aData

Definition at line 84 of file oagFpgaVerilogSynthesis.h. Referenced by oagFpga::VerilogSynthesis::synthesizeIf(), and oagFpga::VerilogSynthesis::synthesizeModuleFunc().

map<oa::oaModBitNet*, MultiRef> oagFpga::VerilogSynthesis::ProceduralState::aLoad

Definition at line 86 of file oagFpgaVerilogSynthesis.h. Referenced by oagFpga::VerilogSynthesis::synthesizeIf(), and oagFpga::VerilogSynthesis::synthesizeModuleFunc().

map<oa::oaModBitNet*, MultiRef> oagFpga::VerilogSynthesis::ProceduralState::blockingAssignments

Definition at line 63 of file oagFpgaVerilogSynthesis.h. Referenced by oagFpga::VerilogSynthesis::getContextualValue(), oagFpga::VerilogSynthesis::synthesizeBlockingassignment(), oagFpga::VerilogSynthesis::synthesizeCase(), oagFpga::VerilogSynthesis::synthesizeCaseEasy(), oagFpga::VerilogSynthesis::synthesizeIf(), and oagFpga::VerilogSynthesis::synthesizeModuleFunc().

MultiRef oagFpga::VerilogSynthesis::ProceduralState::curTrigger

Definition at line 80 of file oagFpgaVerilogSynthesis.h. Referenced by oagFpga::VerilogSynthesis::synthesizeIf().

set<oa::oaModBitNet*> oagFpga::VerilogSynthesis::ProceduralState::dependencies

Definition at line 62 of file oagFpgaVerilogSynthesis.h.

map<string, FunctionVariableAssignment> oagFpga::VerilogSynthesis::ProceduralState::functionAssignments

Definition at line 67 of file oagFpgaVerilogSynthesis.h. Referenced by oagFpga::VerilogSynthesis::synthesizeBlockingassignment().

bool oagFpga::VerilogSynthesis::ProceduralState::isFunction

Definition at line 66 of file oagFpgaVerilogSynthesis.h. Referenced by oagFpga::VerilogSynthesis::evaluateExpression(), oagFpga::VerilogSynthesis::evaluateLval(), and oagFpga::VerilogSynthesis::synthesizeBlockingassignment().

bool oagFpga::VerilogSynthesis::ProceduralState::isRegister

Definition at line 65 of file oagFpgaVerilogSynthesis.h. Referenced by oagFpga::VerilogSynthesis::synthesizeIf(), and oagFpga::VerilogSynthesis::synthesizeModuleFunc().

set<oa::oaModBitNet*> oagFpga::VerilogSynthesis::ProceduralState::negTriggers

Definition at line 69 of file oagFpgaVerilogSynthesis.h. Referenced by oagFpga::VerilogSynthesis::isAsynchronousSignal(), and oagFpga::VerilogSynthesis::synthesizeModuleFunc().

map<oa::oaModBitNet*, MultiRef> oagFpga::VerilogSynthesis::ProceduralState::nonblockingAssignments

Definition at line 63 of file oagFpgaVerilogSynthesis.h. Referenced by oagFpga::VerilogSynthesis::synthesizeCase(), oagFpga::VerilogSynthesis::synthesizeCaseEasy(), oagFpga::VerilogSynthesis::synthesizeIf(), oagFpga::VerilogSynthesis::synthesizeModuleFunc(), and oagFpga::VerilogSynthesis::synthesizeNonblockingassignment().

set<oa::oaModBitNet*> oagFpga::VerilogSynthesis::ProceduralState::nonClockTriggers

Definition at line 72 of file oagFpgaVerilogSynthesis.h. Referenced by oagFpga::VerilogSynthesis::isAsynchronousSignal(), and oagFpga::VerilogSynthesis::synthesizeModuleFunc().

set<oa::oaModBitNet*> oagFpga::VerilogSynthesis::ProceduralState::normalTriggers

Definition at line 69 of file oagFpgaVerilogSynthesis.h. Referenced by oagFpga::VerilogSynthesis::synthesizeModuleFunc().

set<oa::oaModBitNet*> oagFpga::VerilogSynthesis::ProceduralState::posTriggers

Definition at line 69 of file oagFpgaVerilogSynthesis.h. Referenced by oagFpga::VerilogSynthesis::isAsynchronousSignal(), and oagFpga::VerilogSynthesis::synthesizeModuleFunc().

PStateType oagFpga::VerilogSynthesis::ProceduralState::pStateType

Definition at line 77 of file oagFpgaVerilogSynthesis.h. Referenced by oagFpga::VerilogSynthesis::synthesizeIf().

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The documentation for this class was generated from the following file:

• oagFpgaVerilogSynthesis.h

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