oagFpgaVerilogSynthesis.h

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#if !defined(oagFpgaVerilogSynthesis_P)
#define oagFpgaVerilogSynthesis_P

#include "oaDesignDB.h"
//#include "oagAiGraph.h"
#include "oagFpga.h"
#include "oagFpgaMultiRef.h"
#include "oagFpgaVerilogDesign.h"
#include "oagFpgaManager.h"
#include "oagFpgaSynthesis.h"
#include <list>
#include <set>
#include <string>

using namespace std;

namespace oagFpga {

// *****************************************************************************
// VerilogSynthesis
//
//
// *****************************************************************************

class VerilogSynthesis : public Synthesis {

    static const bool IMPLICIT_NET_WARNINGS = false;

    protected:

        // *********************************************************************
        // Type definitions for various Verilog objects.
        // *********************************************************************

        typedef map<string, ConstantValue> ParameterValues;

        class FunctionVariableAssignment : public map<int, MultiRef> {
            public:

                int     start, stop;

                FunctionVariableAssignment() { start = stop = 0; }
                FunctionVariableAssignment(int st, int sp) { start = st; stop = sp; }
        };

        // *********************************************************************
        // ProceduralState
        //
        //
        // *********************************************************************
        
        class ProceduralState {

            public:
                set<oa::oaModBitNet*>                   dependencies;
                map<oa::oaModBitNet*, MultiRef>         blockingAssignments,
                                                        nonblockingAssignments;
                bool                                    isRegister;
                bool                                    isFunction;
                map<string, FunctionVariableAssignment> functionAssignments;

                set<oa::oaModBitNet*>                   normalTriggers, 
                                                        posTriggers, 
                                                        negTriggers;
                set<oa::oaModBitNet*>                   nonClockTriggers;

                // Differeciate synchronous and asynchronous signals
                // (applicable only to IF scope
                typedef enum { PSTATE_SYNC, PSTATE_ASYNC } PStateType;
                PStateType                              pStateType;
                // the asynchronous trigger in the condition of the current IF
                // statement
                MultiRef                                curTrigger;

                // data of the asynchronous LOAD (applicable only when the ALOAD
                // for this net exists)
                map<oa::oaModBitNet*, MultiRef>         aData;
                // the asynchronous LOAD signal associated with this net 
                map<oa::oaModBitNet*, MultiRef>         aLoad;

                ProceduralState()
                {
                    isRegister = false;
                    isFunction = false;
                    pStateType = PSTATE_SYNC;
                }
        };

        // *********************************************************************
        // ConditionalLvalRef
        //
        //
        // *********************************************************************

        class ConditionalLvalRef {
            public:

                oa::oaModBitNet*    lval;
                MultiRef            condition;
                ConditionalLvalRef(oa::oaModBitNet *n, MultiRef c) 
                { 
                    lval = n; condition = c; 
                }
        };

        typedef enum{LVAL_UNKNOWN, LVAL_UNCONDITIONAL, LVAL_CONDITIONAL,
            LVAL_FUNCTION} LvalType;

        // *********************************************************************
        // LvalRef 
        // 
        //
        // *********************************************************************

        class LvalRef {
            public:
                LvalType                 type;

                oa::oaModBitNet*         unconditionalLval;
                list<ConditionalLvalRef> conditionalLval;
                string                   functionLvalName;
                int                      functionLvalBit;

                LvalRef(string c, int b); 
                LvalRef(oa::oaModBitNet* n);
                LvalRef();
                void addConditional(oa::oaModBitNet *n, MultiRef c);
        };

        typedef list<LvalRef*> LvalRefBus;

        // *********************************************************************

    public:

        static void synthesize(VerilogDesign *design);

    protected:

        // synthesize particular subcomponents
        static void synthesizeModule(VerilogDesign::Module *module,
                list<ConstantValue> &parameters);
        static void synthesizeModuleNets();
        static void synthesizeModuleTerms();
        static void synthesizeModuleAssigns();
        static void synthesizeModuleInsts();
        static void synthesizeModuleFunc();
        static void synthesizeBehavioral(VerilogDesign::Statement *statement, 
                ProceduralState &state, ParameterValues *parameters);
        static void synthesizeBlock(VerilogDesign::Statement *statement, 
                ProceduralState &state, ParameterValues *parameters);
        static void synthesizeIf(VerilogDesign::Statement *statement, 
                ProceduralState &state, ParameterValues *parameters);
        static bool synthesizeCaseEasy(VerilogDesign::Statement *statement, 
                ProceduralState &state, ParameterValues *parameters);
        static void synthesizeCase(VerilogDesign::Statement *statement, 
                ProceduralState &state, ParameterValues *parameters);
        static void synthesizeBlockingassignment(
                VerilogDesign::Statement *statement, 
                ProceduralState &state, ParameterValues *parameters);
        static void synthesizeNonblockingassignment(
                VerilogDesign::Statement *statement, 
                ProceduralState &state, ParameterValues *parameters);

        static string getParameterizedModuleName(VerilogDesign::Module *vModule, 
                list<ConstantValue> &parameters);

        // parse expression trees
        static void evaluateConstantExpression(ConstantValue &result, 
                VerilogDesign::Expression *expression,
                ParameterValues *parameters);
        static bool isConstantExpression(VerilogDesign::Expression *expression, 
                ParameterValues *parameters);
        static bool evaluateExpression(MultiRefBus &result, 
                VerilogDesign::Expression *expression, 
                ProceduralState *state, ParameterValues *parameters);
        static void evaluateLval(LvalRefBus &result, 
                VerilogDesign::Expression *expression, 
                ProceduralState *state, ParameterValues *parameters);
        static MultiRef getContextualValue(oa::oaModBitNet *net, 
                ProceduralState *state);

        // utility
        static void appendSuffix(string &root, const string suffix);
        static bool isAsynchronousSignal(oa::oaModBitNet* net, 
                ProceduralState* state);
        static string printBitNetName(oa::oaModBitNet *n);


        // The names of the finished modules
        static set<string>              finishedModules;

        static VerilogDesign::Module    *currentVmodule;
        static ParameterValues          *currentParams;

        static map<string, Bounds>      twoDimRegisters;


};
    
}

#endif

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