oagFpgaVerilogWriter.cpp File Reference

#include "oaDesignDB.h"
#include "oagFpga.h"
#include "oagFpgaManager.h"
#include "oagFpgaModGraph.h"
#include <list>
#include <string>
#include <fstream>
#include "oagFpgaDebug.h"

Include dependency graph for oagFpgaVerilogWriter.cpp:

Go to the source code of this file.

Namespaces
namespace	oagFpga
Functions
string	getBaseName (oa::oaName &name)
	Returns the identifier (without range) of a net.
void	writeNetDef (stringstream &ss, oa::oaModNet *net)
	Writes a net in a Verilog net definition.
string	refToVerilogName (ModRef ref)
	Generates a Verilog net name for a ModRef.
string	BBRefToVerilogName (BBRef ref)
	Generates a Verilog net name for a BBRef.
void	writeBBNodeToVerilog (ofstream &outFile, ModRef x)
	Write a black box node (indexed by x) to a Verilog primitive.
void	writePrimitiveBlackBoxs (const char *filename)
	Write the Verilog entity definition of the black box primitives defined in verilogWriterPrimitives.
Variables
map< string, ModRef >	verilogWriterPrimitives

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Function Documentation

string BBRefToVerilogName (  BBRef  ref  )

Generates a Verilog net name for a BBRef. The name of a BBRef with Ref XXX will be "bb_XXX". The constant string NULL_ASSIGNMENT can be modified to adjust the default Verilog assignment of null references. Parameters: ref  Returns: name Definition at line 157 of file oagFpgaVerilogWriter.cpp. Referenced by oagFpga::writeBBNodeToVerilog().

string getBaseName (  oa::oaName &  name  )

Returns the identifier (without range) of a net. The supplied net can be scalar, a vector bit, or a vector net. Parameters: name  the net name Returns: string Definition at line 28 of file oagFpgaVerilogWriter.cpp. Referenced by oagFpga::writeVerilog().

string refToVerilogName (  ModRef  ref  )

Generates a Verilog net name for a ModRef. The name of a ModRef with Ref XXX will be "bb_XXX". The constant string NULL_ASSIGNMENT can be modified to adjust the default Verilog assignment of null references. Parameters: ref  Returns: name Definition at line 129 of file oagFpgaVerilogWriter.cpp. References oagFpga::ModRef::ref. Referenced by oagFpga::writeBBNodeToVerilog(), and oagFpga::writeVerilog().

void writeBBNodeToVerilog (  ofstream &  outFile, ModRef  x )

Write a black box node (indexed by x) to a Verilog primitive. Definition at line 177 of file oagFpgaVerilogWriter.cpp. References oagFpga::BBRef, oagFpga::BBRefToVerilogName(), oagFpga::refToVerilogName(), and oagFpga::verilogWriterPrimitives. Referenced by oagFpga::writeVerilog().

void writeNetDef (  stringstream &  ss, oa::oaModNet *  net )

Writes a net in a Verilog net definition. This function is needed because bus net definitions have the range declaration before the identifier, unlike their later references inside the module (and the format returned by OpenAccess in the VerilogNS). Parameters: ss  the string stream onto which to append the net definition net  the net Definition at line 75 of file oagFpgaVerilogWriter.cpp. Referenced by oagFpga::writeVerilog().

void writePrimitiveBlackBoxs (  const char *  filename  )

Write the Verilog entity definition of the black box primitives defined in verilogWriterPrimitives. Definition at line 252 of file oagFpgaVerilogWriter.cpp. References oagFpga::verilogWriterPrimitives. Referenced by oagFpga::writeVerilog().

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Variable Documentation

map<string, ModRef> oagFpga::verilogWriterPrimitives

Definition at line 14 of file oagFpgaVerilogWriter.cpp. Referenced by oagFpga::writeBBNodeToVerilog(), and oagFpga::writePrimitiveBlackBoxs().

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