oagFpga Namespace Reference

Classes
class	oagFpga::AiModGraph
	Object for manipulating graphs in the module domain view. More...
class	oagFpga::AiModRef
	A reference into an and/inverter graph in a particular Module. More...
class	oagFpga::Manager
	This class manages the functional description of a design. More...
class	oagFpga::FpgaMapper
	A cut-based mapper. More...
struct	oagFpga::FpgaMapper::TableEntry
class	oagFpga::MapperUtils
	A utility class for commonly used mapping-related functions. More...
class	oagFpga::ModGraph
	Object for manipulating graphs in the module domain view. More...
class	oagFpga::ModRef
	A reference into a Black Box graph in a particular Module. More...
class	oagFpga::ModuleCompiler
	Class for synthesizing various design objects into OpenAccess functional designs. AIG is used as the intermediate storage. More...
class	oagFpga::MultiRef
	A reference to a single-bit function, either an oaModBitNet* or an oagFpga::BBRef. More...
class	oagFpga::Observer
	A observer object to intercept save and open calls. More...
class	oagFpga::OccGraph
	Object for manipulating graphs in the occurrence domain view. More...
class	oagFpga::OccRef
	A reference into an and/inverter graph in a particular Occurrence object. More...
class	oagFpga::RtlNode
	The intermediate data structure for storing the structural netlist with black boxes. More...
class	oagFpga::RtlNode::RtlSeqNodeInfo
class	oagFpga::RtlNode::RtlMuxNodeInfo
class	oagFpga::RtlNode::RtlOptNodeInfo
class	oagFpga::RtlGraph
	The intermediate data structure for storing the structural netlist with black boxes. More...
class	oagFpga::SimMod
	An object for simulating input vectors on hierarchical designs. More...
class	oagFpga::Synthesis
	Class for synthesizing various design objects into OpenAccess functional designs. More...
struct	oagFpga::Synthesis::ConstantValue
struct	oagFpga::Synthesis::Bounds
class	oagFpga::VerilogDesign
	An entire Verilog design. More...
class	oagFpga::VerilogDesign::Module
	A single Verilog module. More...
class	oagFpga::VerilogDesign::Declaration
	A wire, port, reg, or data type declaration. More...
class	oagFpga::VerilogDesign::Function
	A function definition. More...
class	oagFpga::VerilogDesign::Port
	A port definition (from inside a portlist). More...
class	oagFpga::VerilogDesign::Trigger
	A procedural trigger. More...
class	oagFpga::VerilogDesign::Assignment
	A continuous assignment. More...
class	oagFpga::VerilogDesign::AlwaysBlock
	An always block. More...
class	oagFpga::VerilogDesign::Case
	A single case inside of a case statement. More...
class	oagFpga::VerilogDesign::Statement
	A procedural statement. More...
class	oagFpga::VerilogDesign::Instantiation
	A module instantiation. More...
class	oagFpga::VerilogDesign::PortConnection
	A port connection inside of a module instantiation. More...
class	oagFpga::VerilogDesign::Expression
	An expression. More...
class	oagFpga::VerilogDesign::Primary
	An expression primary. More...
class	oagFpga::VerilogDesign::Bundle
	A concatenation of expressions. More...
class	oagFpga::VerilogSynthesis
	Constructs OpenAccess objects and a functional description from a given VerilogDesign object. More...
class	oagFpga::VerilogSynthesis::FunctionVariableAssignment
class	oagFpga::VerilogSynthesis::ProceduralState
class	oagFpga::VerilogSynthesis::ConditionalLvalRef
class	oagFpga::VerilogSynthesis::LvalRef
	This represents the destination of a left-hand assignment. More...
Reading and writing functional descriptions from other formats
void	readVerilog (oa::oaLib *library, const char *filename)
	Reads a behavioral Verilog description into the netlist view.
void	readVerilog (oa::oaLib *library, const oa::oaScalarName &viewName, const char *filename)
	Reads a behavioral Verilog description.
void	YuTest (oa::oaLib *curLib, oa::oaView *curView, oa::oaModule *currentModule)
void	lutMap (oa::oaLib *curLib, oa::oaView *curView, oa::oaDesign *targetDesign, int lutSize=4, int cutsPerNode=200, bool flatten=false, char *clockNetName=NULL, char *clockTriggerName=NULL, char *resetNetName=NULL, char *resetTriggerName=NULL, char *objectiveName="area")
	Perform cut based technology mapping for LUT based FPGA.
void	writeVerilog (oa::oaLib *library, oa::oaView *view, const char *filename)
	Write an OpenAccess library (and functional descriptions) to a Verilog file.
void	writeVerilog (oa::oaDesign *design, const char *filename)
	Write an OpenAccess design (and functional description) to a Verilog file.
oa::oaModBitNet *	toBitNet (oa::oaModNet *net)
Observer *	observer
	Safely casts an oaModNet* to an oaModBitNet*.
oa::oaLib *	YuTestCurLib
oa::oaView *	YuTestCurView
Typedefs
typedef list< class MultiRef >	MultiRefBus
typedef oa::oaIter< oa::oaOccNet >	OccNetIter
typedef unsigned int	BBRef
typedef list< BBRef >	BBRefBus
Enumerations
enum	MultiRefType { BBREF, NET, NEITHER }
Functions
void	initialize ()
	Initializes Func package. Must be called before any use.
string	getBaseName (oa::oaName &name)
	Returns the identifier (without range) of a net.
void	writeNetDef (stringstream &ss, oa::oaModNet *net)
	Writes a net in a Verilog net definition.
string	refToVerilogName (ModRef ref)
	Generates a Verilog net name for a ModRef.
string	BBRefToVerilogName (BBRef ref)
	Generates a Verilog net name for a BBRef.
void	writeBBNodeToVerilog (ofstream &outFile, ModRef x)
	Write a black box node (indexed by x) to a Verilog primitive.
void	writePrimitiveBlackBoxs (const char *filename)
	Write the Verilog entity definition of the black box primitives defined in verilogWriterPrimitives.
Variables
oa::oaVarDataAppDef< oa::oaDesign > *	streamAppDef
	definitions for application extensions
oa::oaVoidPointerAppDef< oa::oaDesign > *	managerAppDef
oa::oaIntAppDef< oa::oaModBitNet > *	bbRefAppDef
oa::oaIntAppDef< oa::oaModBitNet > *	AiRefAppDef
map< string, ModRef >	verilogWriterPrimitives

---

Typedef Documentation

typedef unsigned int oagFpga::BBRef

Definition at line 18 of file oagFpgaRtlGraph.h. Referenced by oagFpga::Synthesis::assignMultiRef(), oagFpga::RtlGraph::binaryBusInputOutputOpt(), oagFpga::RtlGraph::binaryBusOpt(), oagFpga::ModuleCompiler::compileBBNode(), oagFpga::RtlGraph::constantOne(), oagFpga::RtlGraph::constantZero(), oagFpga::Manager::getNetToBBConnection(), oagFpga::RtlGraph::getNextState(), oagFpga::RtlGraph::getNull(), oagFpga::RtlGraph::getOutputBit(), oagFpga::ModGraph::getPrimaryBBID(), oagFpga::RtlGraph::getTerminalDriver(), oagFpga::RtlGraph::getTransitiveFanin_recursive(), oagFpga::RtlGraph::getTransitiveFanout_recursive(), oagFpga::RtlGraph::hasCombinationalCycle(), oagFpga::RtlGraph::newNode(), oagFpga::Manager::prepareNetToBBConnection(), oagFpga::Manager::print(), oagFpga::RtlGraph::removeFromFanout(), oagFpga::RtlGraph::unaryBusInputOutputOpt(), oagFpga::RtlGraph::unaryBusOpt(), writeBBNodeToVerilog(), and writeVerilog().

typedef list<BBRef> oagFpga::BBRefBus

Definition at line 19 of file oagFpgaRtlGraph.h.

typedef list<class MultiRef> oagFpga::MultiRefBus

Definition at line 19 of file oagFpgaMultiRef.h. Referenced by oagFpga::VerilogSynthesis::evaluateExpression(), oagFpga::VerilogSynthesis::evaluateLval(), oagFpga::VerilogSynthesis::synthesizeBlockingassignment(), oagFpga::VerilogSynthesis::synthesizeCase(), oagFpga::VerilogSynthesis::synthesizeCaseEasy(), oagFpga::VerilogSynthesis::synthesizeIf(), oagFpga::VerilogSynthesis::synthesizeModuleAssigns(), oagFpga::VerilogSynthesis::synthesizeModuleFunc(), oagFpga::VerilogSynthesis::synthesizeModuleInsts(), and oagFpga::VerilogSynthesis::synthesizeNonblockingassignment().

typedef oa::oaIter<oa::oaOccNet> oagFpga::OccNetIter

Definition at line 12 of file oagFpgaOccGraph.cpp. Referenced by oagFpga::OccGraph::getNetToBBConnection().

---

Enumeration Type Documentation

enum MultiRefType

Enumeration values: BBREF  NET  NEITHER  Definition at line 18 of file oagFpgaMultiRef.h.

---

Function Documentation

string BBRefToVerilogName (  BBRef  ref  )

Generates a Verilog net name for a BBRef. The name of a BBRef with Ref XXX will be "bb_XXX". The constant string NULL_ASSIGNMENT can be modified to adjust the default Verilog assignment of null references. Parameters: ref  Returns: name Definition at line 157 of file oagFpgaVerilogWriter.cpp. Referenced by writeBBNodeToVerilog().

string getBaseName (  oa::oaName &  name  )

Returns the identifier (without range) of a net. The supplied net can be scalar, a vector bit, or a vector net. Parameters: name  the net name Returns: string Definition at line 28 of file oagFpgaVerilogWriter.cpp. Referenced by writeVerilog().

void oagFpga::initialize (   )

Initializes Func package. Must be called before any use. Initializes data structures for representing and manipulating functional information. The necessary AppDefs are created in the OpenAccess database. An Observer object is also created to intercept the file I/O operations on objects with functional representations. Definition at line 60 of file oagFpga.cpp. References AiRefAppDef, bbRefAppDef, managerAppDef, observer, and streamAppDef.

void oagFpga::lutMap (  oa::oaLib *  curLib, oa::oaView *  curView, oa::oaDesign *  targetDesign, int  lutSize = 4, int  cutsPerNode = 200, bool  flatten = false, char *  clockNetName = NULL, char *  clockTriggerName = NULL, char *  resetNetName = NULL, char *  resetTriggerName = NULL, char *  objectiveName = "area" )

Perform cut based technology mapping for LUT based FPGA. Parameters: library  library viewName  viewName targetDesign  The design which is gonna be mapped cutsPerNode  The number of cuts per node flatten  True if one needs to decompose the whole hierachy, false otherwise clockNet  The specified clock net, NULL if it's not specified clockTrigger  The specified clock trigger, NULL if it's not specified resetNet  The specified clock net, NULL if it's not specified resetTrigger  The specified clock trigger, NULL if it's not specified objective  Can be delay/area Definition at line 200 of file oagFpga.cpp. References oagFpga::MapperUtils::addGlobalClock(), oagFpga::MapperUtils::addGlobalReset(), oagFpga::MapperUtils::createLut(), oagFpga::MapperUtils::createSeq(), oagFpga::FpgaMapper::mapUtils, oagFpga::MapperUtils::printGateUsage(), oagFpga::MapperUtils::removeDanglingNets(), oagFpga::FpgaMapper::techmapArea(), oagFpga::FpgaMapper::techmapDelay(), YuTestCurLib, and YuTestCurView.

void oagFpga::readVerilog (  oa::oaLib *  library, const oa::oaScalarName &  viewName, const char *  filename )

Reads a behavioral Verilog description. Parameters: library  the library in which to find/create the cells described in the file view  the view in which to find/create the cells filename  the path of the Verilog file to read Definition at line 109 of file oagFpga.cpp. References oagFpgaVerilog_yydesign, oagFpgaVerilog_yyfilename, oagFpgaVerilog_yyin, and oagFpgaVerilog_yyparse(). Referenced by readVerilog().

void oagFpga::readVerilog (  oa::oaLib *  library, const char *  filename )

Reads a behavioral Verilog description into the netlist view. A view other than "netlist" can be specified with additional parameters. Parameters: library  the library in which to find/create the cells described in the file filename  the path of the Verilog file to read Definition at line 86 of file oagFpga.cpp. References readVerilog().

string refToVerilogName (  ModRef  ref  )

Generates a Verilog net name for a ModRef. The name of a ModRef with Ref XXX will be "bb_XXX". The constant string NULL_ASSIGNMENT can be modified to adjust the default Verilog assignment of null references. Parameters: ref  Returns: name Definition at line 129 of file oagFpgaVerilogWriter.cpp. References oagFpga::ModRef::ref. Referenced by writeBBNodeToVerilog(), and writeVerilog().

oa::oaModBitNet* toBitNet (  oa::oaModNet *  net  )  [inline]

If the given net has multiple bits, an assertion will be generated. Definition at line 87 of file oagFpga.h. Referenced by oagFpga::ModGraph::connectEquivalentNetsInGraph(), oagFpga::AiModGraph::connectEquivalentNetsInGraph(), oagFpga::OccGraph::getAllConnections(), oagFpga::OccGraph::getInputs(), oagFpga::AiModGraph::getInputs(), oagFpga::OccGraph::getNetToBBConnection(), oagFpga::OccGraph::getOutputs(), oagFpga::ModGraph::getOutputs(), oagFpga::AiModGraph::getOutputs(), oagFpga::MapperUtils::identifyControls(), oagFpga::MapperUtils::mergeEquivalentNets(), oagFpga::Manager::print(), oagFpga::MapperUtils::removeDanglingNets(), and writeVerilog().

void writeBBNodeToVerilog (  ofstream &  outFile, ModRef  x )

Write a black box node (indexed by x) to a Verilog primitive. Definition at line 177 of file oagFpgaVerilogWriter.cpp. References BBRef, BBRefToVerilogName(), refToVerilogName(), and verilogWriterPrimitives. Referenced by writeVerilog().

void writeNetDef (  stringstream &  ss, oa::oaModNet *  net )

Writes a net in a Verilog net definition. This function is needed because bus net definitions have the range declaration before the identifier, unlike their later references inside the module (and the format returned by OpenAccess in the VerilogNS). Parameters: ss  the string stream onto which to append the net definition net  the net Definition at line 75 of file oagFpgaVerilogWriter.cpp. Referenced by writeVerilog().

void writePrimitiveBlackBoxs (  const char *  filename  )

Write the Verilog entity definition of the black box primitives defined in verilogWriterPrimitives. Definition at line 252 of file oagFpgaVerilogWriter.cpp. References verilogWriterPrimitives. Referenced by writeVerilog().

void oagFpga::writeVerilog (  oa::oaDesign *  design, const char *  filename )

Write an OpenAccess design (and functional description) to a Verilog file. The Verilog description will be appended to the end of the file. Modules, instances, scalar nets, bus nets, and ports/terminals are mapped directly from OpenAccess database objects to Verilog Nets which are undriven by a signal but marked equivalent (through the OpenAccess markEquivalent method) to another net that is driven by a signal will be assigned using a direct Verilog "assign" All BB and TERMINAL nodes are mapped to new Verilog nets names "bb_XXX" where XXX is the Ref of the node. The functionality is described using primivtive instantiation, one per BB node If there are pre-existing OpenAccess nets of a conflicting name "bb_XXX", an error will be generated. Parameters: design  filename  Definition at line 320 of file oagFpgaVerilogWriter.cpp. References BBRef, getBaseName(), oagFpga::ModRef::ref, refToVerilogName(), toBitNet(), writeBBNodeToVerilog(), and writeNetDef(). Referenced by writeVerilog().

void oagFpga::writeVerilog (  oa::oaLib *  lib, oa::oaView *  view, const char *  filename )

Write an OpenAccess library (and functional descriptions) to a Verilog file. The Verilog descriptions will be appended to the end of the file. Parameters: lib  filename  Definition at line 605 of file oagFpgaVerilogWriter.cpp. References writePrimitiveBlackBoxs(), and writeVerilog().

void oagFpga::YuTest (  oa::oaLib *  curLib, oa::oaView *  curView, oa::oaModule *  currentModule )

Definition at line 160 of file oagFpga.cpp.

---

Variable Documentation

oa::oaIntAppDef< oa::oaModBitNet > * oagFpga::AiRefAppDef

Definition at line 40 of file oagFpga.cpp. Referenced by oagFpga::ModuleCompiler::compileBBNode(), oagFpga::Manager::create(), oagFpga::Manager::destroy(), oagFpga::Manager::getNetToAiConnection(), initialize(), oagFpga::Manager::prepareNetToAiConnection(), oagFpga::Manager::removeNetToAiConnection(), and oagFpga::Manager::setNetToAiConnection().

oa::oaIntAppDef< oa::oaModBitNet > * oagFpga::bbRefAppDef

Definition at line 38 of file oagFpga.cpp. Referenced by oagFpga::Synthesis::assignMultiRef(), oagFpga::Synthesis::binaryBusInputOutputOpt(), oagFpga::Synthesis::binaryBusOpt(), oagFpga::Synthesis::binaryOpt(), oagFpga::Manager::create(), oagFpga::Synthesis::createModule(), oagFpga::Manager::destroy(), oagFpga::Manager::getNetToBBConnection(), initialize(), oagFpga::Synthesis::latch(), oagFpga::Synthesis::mux(), oagFpga::Synthesis::notOf(), oagFpga::Manager::prepareNetToBBConnection(), oagFpga::Synthesis::seq(), oagFpga::Manager::setNetToBBConnection(), oagFpga::Synthesis::unaryBusInputOutputOpt(), and oagFpga::Synthesis::unaryBusOpt().

oa::oaVoidPointerAppDef< oa::oaDesign > * oagFpga::managerAppDef

Definition at line 36 of file oagFpga.cpp. Referenced by oagFpga::ModuleCompiler::compileModules(), oagFpga::Manager::create(), oagFpga::Synthesis::createModule(), oagFpga::Manager::destroy(), oagFpga::Manager::get(), oagFpga::Manager::hasManager(), initialize(), and oagFpga::Manager::Manager().

Observer * oagFpga::observer

Safely casts an oaModNet* to an oaModBitNet*. Definition at line 42 of file oagFpga.cpp. Referenced by initialize().

oa::oaVarDataAppDef< oa::oaDesign > * oagFpga::streamAppDef

definitions for application extensions Definition at line 34 of file oagFpga.cpp. Referenced by initialize(), oagFpga::Observer::onFirstOpen(), oagFpga::Observer::onPostSave(), and oagFpga::Observer::onPreSave().

map<string, ModRef> oagFpga::verilogWriterPrimitives

Definition at line 14 of file oagFpgaVerilogWriter.cpp. Referenced by writeBBNodeToVerilog(), and writePrimitiveBlackBoxs().

oa::oaLib * oagFpga::YuTestCurLib

Definition at line 156 of file oagFpga.cpp. Referenced by lutMap().

oa::oaView * oagFpga::YuTestCurView

Definition at line 157 of file oagFpga.cpp. Referenced by lutMap().

---