oagFpgaVerilogWriter.cpp

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#include "oaDesignDB.h"
#include "oagFpga.h"
#include "oagFpgaManager.h"
#include "oagFpgaModGraph.h"
#include <list>
#include <string>
#include <fstream>

#include "oagFpgaDebug.h"

namespace oagFpga {

map<string, ModRef> verilogWriterPrimitives;

// *****************************************************************************
// getBaseName()
//
//
// *****************************************************************************
string
getBaseName(oa::oaName &name) {

  oa::oaString str;  
  const oa::oaVerilogNS verilogNS;

  switch(name.getType()) {
  case oa::oacScalarNameType: {
    oa::oaScalarName *scalarName = name.getScalar();
    assert(scalarName);
    scalarName->get(verilogNS, str);
    return string(str);
  }
  case oa::oacVectorNameType: {
    oa::oaVectorName *vectorName = name.getVector();
    assert(vectorName);
    vectorName->getBaseName(verilogNS, str);
    return string(str);
  }
  case oa::oacVectorBitNameType: {
    oa::oaVectorBitName *vectorBitName = name.getVectorBit(); 
    assert(vectorBitName);
    vectorBitName->getBaseName(verilogNS, str);
    return string(str);
  }          
  default:
    cerr << "ERROR: Unsupported name type" << endl;
    QUIT_ON_ERROR;
  }

  return string("");
}


// *****************************************************************************
// writeNetDef()
//
//
// *****************************************************************************
void
writeNetDef(stringstream & ss, oa::oaModNet *net) {
  assert(net);
  
  oa::oaString str;
  const oa::oaVerilogNS verilogNS;

  oa::oaName name;
  net->getName(name);
  switch(name.getType()) {
  case oa::oacScalarNameType: {
    oa::oaScalarName *scalarName = name.getScalar();
    assert(scalarName);
    scalarName->get(verilogNS, str);
    ss << str;
    break;
  }
  case oa::oacVectorNameType: {
    oa::oaVectorName *vectorName = name.getVector();
    assert(vectorName);
    ss << "[" << vectorName->getStart()
       << ":" << vectorName->getStop() << "] ";
    vectorName->getBaseName(verilogNS, str);
    ss << str;    
    break;
  }
  case oa::oacVectorBitNameType: {
    oa::oaVectorBitName *vectorBitName = name.getVectorBit(); 
    assert(vectorBitName);
    ss << "[" << vectorBitName->getIndex() << "] ";
    vectorBitName->getBaseName(verilogNS, str);
    ss << str; 
    break;
  }          
  default:
    cerr << "ERROR: Unsupported name type" << endl;
    QUIT_ON_ERROR;
  }
}

// *****************************************************************************
// refToVerilogName()
//
//
// *****************************************************************************
string
refToVerilogName(ModRef ref) {
  // const char *NULL_ASSIGNMENT = "1'b0";
  const char *NULL_ASSIGNMENT = "1'bx";

  stringstream result;
  if (ModGraph::isNull(ref)) {
    result << NULL_ASSIGNMENT;
  } else {
    result << "bb_" << ref.ref;
  }
  return result.str();
}

// *****************************************************************************
// BBRefToVerilogName()
//
//
// *****************************************************************************
string
BBRefToVerilogName(BBRef ref) {
  // const char *NULL_ASSIGNMENT = "1'b0";
  const char *NULL_ASSIGNMENT = "1'bx";

  stringstream result;
  if (RtlGraph::isNull(ref)) {
    result << NULL_ASSIGNMENT;
  } else {
    result << "bb_" << ref;
  }
  return result.str();
}

// *****************************************************************************
// writeBBNodeToVerilog()
//
// *****************************************************************************
void 
writeBBNodeToVerilog(ofstream& outFile, ModRef x) {

    outFile << "\t";

    // Firstly, generate the primitive name

    RtlNode::FuncType type = ModGraph::getNodeType(x);
    stringstream primitiveName;
    switch(type) {
        case RtlNode::CONTROL:
            // So far the MUX is one-bit
            assert(ModGraph::getNumOutputBits(x) == 1);
            primitiveName << "MUX";
            break;
        case RtlNode::OPERATOR: {
            RtlNode::OptType optType = ModGraph::getNodeOptType(x);
            const char* optName = RtlNode::optTypeName[optType];
            primitiveName << optName;
            break;
        }
        case RtlNode::SEQ: {
            // So far the sequential element is one-bit
            assert(ModGraph::getNumOutputBits(x) == 1);
            RtlNode::SeqType seqType = ModGraph::getNodeSeqType(x);
            const char* seqName = RtlNode::seqTypeName[seqType];
            primitiveName << seqName;
            break;
        }
        default:
            cerr << "ERROR: Unknown BB node type" << endl;
            QUIT_ON_ERROR;
    }
    list<ModRef> fanin = ModGraph::getFanin(x);
    primitiveName << "_" << fanin.size() ;

    // setup a symbol list for all black box primitives used
    if(verilogWriterPrimitives.find(primitiveName.str()) ==
            verilogWriterPrimitives.end()){
        verilogWriterPrimitives[primitiveName.str()] = x;
    }

    outFile << primitiveName.str();

    // print instance name
    outFile << " inst_" << BBRefToVerilogName(ModGraph::getPrimaryBBID(x));
   
    outFile << "( ";

    // Then, print input pins

    for(list<ModRef>::iterator refIter = fanin.begin(); refIter != fanin.end();
            ++ refIter){
        outFile << refToVerilogName(*refIter) << ", ";
    }

    // Finally, print output pins according to the width of the outputs of a BB node

    int numOutputBits = ModGraph::getNumOutputBits(x);
    BBRef pID = ModGraph::getPrimaryBBID(x);
    for(BBRef cID = pID; cID < pID+numOutputBits; ++ cID){
        outFile << BBRefToVerilogName(cID);
        if(cID+1<pID+numOutputBits)
            outFile << ", ";
    }

    outFile << " );" << endl;
}

// *****************************************************************************
// writeVerilog()
//
// *****************************************************************************
void
writePrimitiveBlackBoxs(const char* filename) {

    ofstream outFile;
    outFile.open(filename, ios::app); 
    if (!outFile) {
        cerr << "ERROR: Could not open file " << filename << " for output" << endl;
        QUIT_ON_ERROR;
    }

    for(map<string, ModRef>::iterator primIter = verilogWriterPrimitives.begin();
            primIter != verilogWriterPrimitives.end(); ++ primIter) {
        string pName = primIter->first;
        ModRef pID = primIter->second;
        outFile << endl << "// black box module" << endl;
        outFile << "module " << pName << " (";
        int numInputs = ModGraph::getFanin(pID).size();
        for(int i=1;i<=numInputs;i++){
            outFile << "in" << i << ", ";
        }
        int numOutputs = ModGraph::getNumOutputBits(pID);
        for(int i=1;i<=numOutputs;i++){
            outFile << "out" << i;
            if(i<numOutputs)
                outFile << ", ";
        }
        outFile << ");" << endl;
        outFile << "input ";
        for(int i=1;i<=numInputs;i++){
            outFile << "in" << i;
            if(i<numInputs)
                outFile << ", ";
        }
        outFile << ";" << endl;
        outFile << "output ";
        for(int i=1;i<=numOutputs;i++){
            outFile << "out" << i;
            if(i<numOutputs)
                outFile << ", ";
        }
        outFile << ";" << endl;
        outFile << "endmodule" << endl << endl;
    }
}

// *****************************************************************************
// writeVerilog()
//
//
// *****************************************************************************
void            
writeVerilog(oa::oaDesign *design, const char *filename) {
    assert(design);
    assert(filename);

    const oa::oaVerilogNS verilogNS;

    ofstream outFile;
    outFile.open(filename, ios::app); 
    if (!outFile) {
        cerr << "ERROR: Could not open file " << filename << " for output" << endl;
        QUIT_ON_ERROR;
    }

    cerr << "Begin to write output Verilog " << filename << "..." << endl;
    cerr << "Number of BBNodes is " << 
        ModGraph::getGraph(design)->getBBNodeNum() << endl;

    outFile << "// Written by oagFpga Verilog writer" << endl << endl;

    // for each module...
    oa::oaModule *module;
    oa::oaIter<oa::oaModule> moduleIter(design->getModules());
    while((module = moduleIter.getNext())) {
        oa::oaString str;

        // 1. write module definition
        module->getName(verilogNS, str);
        outFile << "module " << str << "(";

        // 1.a. portlist
        bool first = true;
        oa::oaModTerm *term;
        oa::oaIter<oa::oaModTerm> termIter(module->getTerms(oacTermIterNotImplicit));
        while((term = termIter.getNext())) {
            oa::oaName termName, netName;

            term->getNet()->getName(netName);
            term->getName(termName);

            if (!first) {
                outFile << ", ";
            }

            if (getBaseName(termName) == getBaseName(netName)) {
                outFile << getBaseName(termName);
            } else {
                outFile << "." << getBaseName(termName) << "(" 
                    << getBaseName(netName) << ")";
            }

            first = false;
        }
        outFile << ");" << endl;

        // 2. definitions

        // 2.a. inputs/outputs
        outFile << "\t" << "// inputs/outputs" << endl;
        termIter.reset();
        while((term = termIter.getNext())) {
            stringstream ss;
            writeNetDef(ss, term->getNet());
            if(term->getTermType() == oa::oacInputTermType) {
                outFile << "\t" << "input " << ss.str() << ";" << endl;
            } else if(term->getTermType() == oa::oacOutputTermType) {
                outFile << "\t" << "output " << ss.str() << ";" << endl;
            }
        }

        // 2.b. nets
        outFile << "\t" << "// intermediate nets defined " 
            << "in the original Verilog" << endl;
        oa::oaModNet *net;
        oa::oaIter<oa::oaModNet> netIter(module->getNets());
        while((net = netIter.getNext())) {
            // do not write if this is already a terminal
            if (net->getTerms().isEmpty()) {
                stringstream ss;
                writeNetDef(ss, net);
                if (net->getSigType() == oa::oacSignalSigType) {
                    outFile << "\t" << "wire " << ss.str() << ";" << endl;
                } else if (net->getSigType() == oa::oacTieHiSigType) {
                    outFile << "\t" << "supply1 " << ss.str() << ";" << endl;
                }  else if (net->getSigType() == oa::oacTieLoSigType) {
                    outFile << "\t" << "supply0 " << ss.str() << ";" << endl;
                }
            }
        }

        // 2.c. bb graph
        outFile << "\t" << "// intermediate wires/regs due to BBNodes" << endl;
        list<ModRef> outputNodes, all;
        if (Manager::hasManager(module->getDesign())) {
            ModGraph::getOutputs(module, outputNodes);
            ModGraph::getTransitiveFanin(outputNodes, all, true, true);
            all.splice(all.end(), outputNodes);

            for(list<ModRef>::iterator nodeIter = all.begin();
                    nodeIter != all.end(); nodeIter++) {
                ModRef ref = *nodeIter;
                int numOutputBits = ModGraph::getNumOutputBits(ref);
                BBRef pID = ModGraph::getPrimaryBBID(ref);
                // write the declarations for every single bit of a BB node
                for(BBRef cID = pID; cID < pID+numOutputBits; ++ cID){
                    if (ModGraph::isSequential(ref)) {
                        // NOTE: somehow Quartus has trouble for the output
                        // Verilog with these "reg", there should be no
                        // difference between "reg" and "wire" for a structural
                        // Verilog
                        //outFile << "\t" << "reg " << "bb_" << cID << ";" << endl;
                        outFile << "\t" << "wire " << "bb_" << cID << ";" << endl;
                    } else {
                        outFile << "\t" << "wire " << "bb_" << cID << ";" << endl;
                    }
                }
            }
            outFile << endl;
        }      

        // 3. equivalent nets
        outFile << "\t" << "// equivalent nets" << endl;
        oa::oaIter<oa::oaModNet> singleNetIter(module->getNets(oacNetIterSingleBit));
        while((net = netIter.getNext())) {     
            oa::oaModBitNet *bitNet = toBitNet(net);
            oa::oaModBitNet *driverNet = ModGraph::findDriverOfEquivalentNets(bitNet);
            if (driverNet) {
                bitNet->getName(verilogNS, str);
                outFile << "\t" << "assign " << str << " = ";
                driverNet->getName(verilogNS, str);
                outFile << str << ";" << endl;
            }
        }

        // 4. Black box graph
        outFile << "\t" << "// connections due to BB graph" << endl;
        if (Manager::hasManager(module->getDesign())) {

            for(list<ModRef>::iterator nodeIter = all.begin();
                    nodeIter != all.end(); nodeIter++) {
                ModRef ref = *nodeIter;

                // check for naming conflict
                char bbNetString[64];
                int numOutputBits = ModGraph::getNumOutputBits(ref);
                BBRef pID = ModGraph::getPrimaryBBID(ref);
                // check the name for every single bit of a BB node
                for(BBRef cID = pID; cID < pID+numOutputBits; ++ cID){
                    sprintf(bbNetString, "bb_%d", cID);
                    if (oa::oaModScalarNet::find(module, oa::oaScalarName(verilogNS,
                                    bbNetString))) {
                        cerr << "ERROR : Module has pre-existing net of conflicting\
                            name type \"bb_XXX\"" << endl;
                        QUIT_ON_ERROR;
                    }
                }

                if (ModGraph::isTerminal(ref)) {
                    // TERMINAL node

                    oa::oaModBitNet *net = ModGraph::getNetToBBConnection(ref);
                    if (net) {
                        net->getName(verilogNS, str);
                    }

                    ModRef driver = ModGraph::getTerminalDriver(ref);
                    if (!ModGraph::isNull(driver)) {
                        // driven by another node            
                        outFile << "\t" << "assign " << bbNetString << " = " 
                            << refToVerilogName(driver) << ";" << endl;

                        if (net && net->getSigType() == oa::oacSignalSigType) {
                            // net driven by terminal
                            outFile << "\t" << "assign " << str << " = " 
                                << "bb_" << ref.ref << ";" << endl;
                        }

                    } else if (net) {
                        // driven by net
                        outFile << "\t" << "assign " << bbNetString 
                            << " = " << str << ";" << endl;
                    } else {
                        // driven by nothing
                        cerr << "WARNING: BB Node " << ref.ref << " is driven by\
                            nothing" << endl;
                    }

                } else if (ModGraph::isFunctional(ref) ||
                        ModGraph::isSequential(ref)) {
                    writeBBNodeToVerilog(outFile, ref);

                } else if (ref == ModGraph::constantZero(module)) {
                    outFile << "\t" << "assign " << bbNetString << " = 1'b0;" << endl;
                } else if (ref == ModGraph::constantOne(module)) {
                    outFile << "\t" << "assign " << bbNetString << " = 1'b1;" << endl;
                }

            }
        }

        // 5. module instantiations
        oa::oaModInst *inst;
        oa::oaIter<oa::oaModInst> instIter(module->getInsts());
        while((inst = instIter.getNext())) {
            oa::oaModule *master = inst->getMasterModule();
            if (!master) {
                cerr << "ERROR: Could not bind to master module" << endl;
                QUIT_ON_INTERNAL_ERROR;
            }
            master->getName(verilogNS, str);
            outFile << "\t" << str << " ";

            inst->getName(verilogNS, str);
            outFile << str << " (";

            // are the connections by name or position?
            bool first = true;
            if (inst->usesTermPositions()) {
                // connected by position

                set<int> validPositions;
                oa::oaModInstTerm *instTerm;
                oa::oaIter<oa::oaModInstTerm> instTermIter(inst->getInstTerms());
                while((instTerm = instTermIter.getNext())) {
                    validPositions.insert(instTerm->getTermPosition());
                }
                for(int i=*(validPositions.begin()); i<=*(validPositions.rbegin()); i++) {
                    assert(validPositions.find(i) != validPositions.end());
                    instTerm = oa::oaModInstTerm::find(inst, i);
                    assert(instTerm);
                    if (!first) {
                        outFile << ", ";
                    }
                    oa::oaModNet *net = instTerm->getNet();
                    if (net) {
                        first = false;
                        net->getName(verilogNS, str);
                        outFile << str;
                    } else {
                        outFile << " "; // no assignment
                    }
                }

            } else {
                // connected by name

                oa::oaModInstTerm *instTerm;
                oa::oaIter<oa::oaModInstTerm> instTermIter(inst->getInstTerms());
                while((instTerm = instTermIter.getNext())) {
                    oa::oaModNet *net = instTerm->getNet();
                    if (net) {
                        if (!first) {
                            outFile << ", ";
                        }
                        first = false;

                        oa::oaName termName;
                        instTerm->getTermName(termName);
                        net->getName(verilogNS, str);
                        outFile << "." << getBaseName(termName) << "(" << str << ")";
                    }
                }
            }

            outFile << ");" << endl;
        }

        outFile << "endmodule" << endl << endl;
    }

    outFile.close();
}


// *****************************************************************************
// writeVerilog()
//
//
// *****************************************************************************
void            
writeVerilog(oa::oaLib *lib, oa::oaView *view, const char *filename) {
    assert(lib);
    assert(filename);
    assert(view);

    oa::oaScalarName libName;
    lib->getName(libName);
    oa::oaScalarName viewName;
    view->getName(viewName);

    oa::oaCellView *cellView;
    oa::oaIter<oa::oaCellView> cellViewIter(view->getCellViews());
    while((cellView = cellViewIter.getNext())) {
        oa::oaScalarName cellName;
        cellView->getCell()->getName(cellName);

        oa::oaDesign *design = oa::oaDesign::find(libName, cellName, viewName);
        if (design) {
            writeVerilog(design, filename);
        }
    }
    writePrimitiveBlackBoxs(filename);
}

}

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