Projects

University of California Los Angeles
Design Automation Laboratory

Primary investigator (PI)

Design and Design Automation of Mixed-Signal Circuits

Primary investigator (PI)

Prof. Lei He
Prof. Sudhakar Pamarti

Attended students

Hao Yu (now assistant professor at Singapore Nanyang Technological University)
Jun Chen (now SI leader at Mindspeed)
Yiyu Shi (now assistant professor at Missouri University of Science and Technology)
Wei Yao
Fang Gong
Wei Wu
Hyungsoo Kim
Sina Basir-Kazeruni

Funding sources
SRC "RINGS: Reconfiguration for Embedded Systems," 2003/9-2007/12

SRC "Crosstalk Insensitive Electrical Signaling for Wired Data Communications," 2008/4 - 2011/3

UC MICRO'06&07 "Circuit Optimization for Robustness and Power Efficiency"

UC MICRO'06&07 "Beyond the die signal integrity"

Research Statement

We design analog circuits for high-speed crosstalk insensitive signaling, field programmable RF interconnect carrying multiple logic channels by one wire, and DC/DC converter. In addition, we also develop behavioral modeling, simulation and design methodology for these analog circuits.

System-in-Package and 3D integration

Variation Aware Modeling and Design

Research Outcomes

SRAM Yield Modeling by Probability Collectives. Importance sampling is a popular approach to estimate rare event failures of SRAM cells. We propose to improve importance sampling by probability collectives. First, we use "Kullback-Leibler (KL) distance" to measure the distance between the optimal sampling distribution and the original sampling distribution of variable process parameters. Further, the probability collectives (PC) technique using immediate sampling is adapted to analytically minimize the KL distance and to obtain a sampling distribution as close to the optimal as possible. The proposed algorithm signi?cantly accelerates the convergence of importance sampling. Experiments demonstrate that proposed algorithm is 5200X faster than the Monte Carlo approach and achieves more than 40X speedup over other existing state-of-the-art techniques without compromising estimation accuracy. This work was presented at ISPD'12[C153]

Non-Monte-Carlo Transient Noise Analysis. Stochastic device noise has become a significant challenge for high-precision analog/RF circuits, and it is particularly difficult to correctly include both white noise and flicker noise into the traditional transient verification flow with efficient numerical solution. In this paper, a Non-Monte-Carlo transient noise analysis is developed. Both white noise and flicker noise are considered in the Ito integral based stochastic differential algebraic equation (SDAE), which is further solved with one-time calculation of variance using the stochastic orthogonal polynomials (SoPs). This work is the first to provide SoP based SDAE solution with application in transient noise analysis. Experiments on a number of different analog circuits demonstrate that the proposed method is up to 488X faster than Monte Carlo method with a similar accuracy, and achieves on average 6.8X speedup over existing non-Monte-Carlo approaches. This work was presented at DAC'11 [C143]

Stochastic Analog Circuit Behavior Modeling. Stochastic device parameter variations have dramatically increased beyond the scale of 65nm and can significantly lead to large mismatch for analog circuits. To estimate unknown analog circuit behavior in performance space under the given stochastic variations in parameter space, many state-of-art approaches have been developed recently. However, either Gaussian distribution or response surface model (RSM) with analytical formulae has to be assumed when connecting performance space and parameter space. A novel point-estimation based approach has been proposed in this paper to capture arbitrary stochastic distributions for analog circuit behaviors in performance space. First, to evaluate high-order moments of circuit behavior in an accurate fashion, the point-estimation method has been applied with only a few number of simulations. Then, probability density function (PDF) of circuit behavior can be efficiently extracted by the obtained high-order moments. This method is further extended for multiple parameters under linear complexity. Extensive numerical experiments on a number of different circuits have demonstrated that the proposed point-estimation method can provide up to 181X runtime speedup with the same accuracy, when compared with Monte Carlo method. Moreover, it can further achieve up to 15X speedup over the RSM-based method such as APEX with the similar accuracy. This work was presented at ISPD'11 [C142]

QuickYield. . With technology scaling down to 90nm and below, many yield-driven design and optimization methodologies have been proposed to com- bat the prominent process variation and to increase the yield. A critical issue that impacts the efficiency of all those methods is to estimate the yield given the design parameters under variation. Ex- isting methods either use Monte Carlo approach in performance do- main where thousands of simulations are required, or uses iterative search in parameter domain where a number of simulations are re- quired to characterize each point on the parameter boundary defined by the performance constraints. To improve the efficiency, in this pa- per we propose QuickYield, a direct non-iterative method where each point on the boundary can be obtained by a “one-shot” simulation. Experiments on different circuit instances show that for the same ac- curacy, QuickYield is up to 519X faster compared with the Monte Carlo approach, and up to 4.7X faster compared with YENSS, the fastest approach reported in literature. This work was presented at DAC'10 [C137]

Joint design time and post-silicon optimization for analog circuits. This paper has been an open problem in literature because of the complex nature of analog circuit modeling and optimization. In this paper we formulate the co-optimization problem for digitally tuned analog circuits to optimize the parametric yield, subject to power and area constraints. A general optimization framework combing the branch-and-bound algorithm and gradient ascent method is proposed. We demonstrate our framework with two examples in high-speed serial link, the transmitter design and the phase-locked-loop (PLL) design. Simulation results show that compared with the design heuristic from analog designers' perspective, joint design-time and post-silicon optimization can improve the yield by up to 47% for transmitter design and up to 56% for PLL design under the same area and power constraints. To the best of the authors' knowledge, this is the first yield-driven analog circuit design technique that optimizes post-silicon tuning together with the design-time optimization. 4x by carefully handling the generation and propagation of these low frequency signals. This work was presented at ICCAD'09 [C129]

Worst Case Noise for Differential Signaling. Differential signaling is widely used in high speed data communications. Inter-symbol interference (ISI) and crosstalk between differential pair, however, heavily affect the integrity of differential signaling as measured by timing jitter and amplitude noise in the eye diagram. To reduce the impact of ISI, a pre-emphasis filter is commonly used, but it increases the crosstalk noise. In this paper, we first propose formula-based jitter and noise models considering the combined effect of ISI, crosstalk, and pre-emphasis filter. With given input patterns, our models achieve within 5% difference compared to SPICE simulation. Moreover, using the formula-based models, we develop mathematical programming algorithms to directly find out the input patterns for worst-case jitter and worst-case amplitude noise. Experiments show our algorithms obtain more reliable worst-case jitter and noise compared to Monte Carlo simulation and reduce runtime by 150X. 4x by carefully handling the generation and propagation of these low frequency signals. This work was presented at ISQED'09 [C124]

Stochastic Current Prediction Enabled Frequency Actuator for Runtime Resonance Noise Reduction. Power delivery network (PDN) is a distributed RLC network with its dominant resonance frequency in the low-to-middle frequency range. Though high-performance chips' working frequencies are much higher than this resonance frequency in general, chip runtime loading frequency is not. When a chip executes a chunk of instructions repeatedly, the induced current load may have harmonic components close to this resonance frequency, causing excessive power integrity degradation. Existing PDN design solutions are, however, mainly targeted at reducing high-frequency noise and not effective to suppress such resonance noise. In this work, we propose a novel approach to proactively suppress this type of noise. A method based on a high dimension generalized Markov process is developed to predict current load variation. Based on such prediction, a clock frequency actuator design is proposed to proactively select an optimal clock frequency to suppress the resonance. To the best of our knowledge, this is the first in-depth study on proactively reducing runtime instruction execution induced PDN resonance noise. This work was presented at ASPDAC'09 [C121]

Scalable Symbolic Model Order Reduction. Symbolic model order reduction (SMOR) is to reduce the com- plexity of a model with symbolic parameters. It is an important problem in analog circuit synthesis and digital circuit modeling with process variations. However, existing symbolic model order reduction (SMOR) methods do not scale well with the number of symbols or with the model order. This paper presents a scalable SMOR algorithm, namely S2MOR. We first separate the original multi-port multi-symbol system into a set of single-port systems by superposition theorem, and then integrate them together to form a lower-bordered block diagonal (LBBD) structured system. Each block is reduced independently, with a stochastic program- ming to distribute the given overall model order between blocks for best accuracy. The entire system is efficiently solved by low- rank update. Compared with existing SMOR algorithms, given the same memory space, S2MOR improves accuracy by up to 78% at a similar reduction time. In addition, the factorization and simulation of the reduced model by S2MOR is up to 17X faster. This work was presented at IEEE Behaviorial Modeling and Simulation Conference 2008 [C120]

Power efficient pulse width modulation DC/DC converters with zero voltage switching control. This paper proposes a power-efficient PWM DC/DC converter design with a novel zero voltage switching (ZVS) control technique. The ZVS control is realized by an inner feedback loop which is implemented by simple digital circuitry between the input and output of the power transistors and achieves real-time zero voltage switching (ZVS) for various loading and device parameters with power efficiencies over 90.0%. In addition, an outer feedback loop is used to ensure that the output precisely tracks a reference voltage level. We have also built the relationship between the output voltage ripple and the speed of the voltage comparators which has shown to introduce new low-frequency signals to the loops and cause significant output voltage ripples. Experiment results show that the output ripple could be reduced by 4x by carefully handling the generation and propagation of these low frequency signals. This work was presented in ISLPED'06 [C92]

Transmission line modeling and synthesis for multi channel communication. To overcome the limitations of traditional interconnects, transmission lines that transmit multi-channel signals via high frequency carriers have recently been proposed and realized for intra-chip and inter-chip communication. We derive a closed-form model for SNR for such interconnects with multiple ports and branches, and propose efficient figures of merit (FOMs) to minimize signal distortion. Experiments show that the SNR model is accurate compared to SPICE simulation and signal distortion FOMs are effective. Using the proposed models, we further automatically synthesize coplanar waveguides for radio-frequency (RF) interconnects with capacitive couplers. We minimize the total interconnect area under constraints of SNR and signal distortion. Compared to the published manual designs, the synthesized solution can reduce up to 80% area. Furthermore, the optimized solutions vary greatly with respect to number of ports, frequency bands, topologies and terminations, and therefore automatic synthesis is needed. This work was presented in BMAS'05 [C75] and TCAD [J24].

Staggered twisted-bundle interconnect for crosstalk and delay reduction. To achieve small delay and low crosstalk for multiple signal nets with capacitive and inductive coupling, we propose in this paper a novel interconnect structure, staggered twisted-bundle wires where groups of twisted wires are staggered. This new structure is different from the previously proposed twisted bundle wires with one group of twisted wires and another group of normal wires. Using accurate circuit models and efficient algorithms to find the worst case noise and delay for comprehensive combinations of signal patterns and a range of arrival times, we assume signal and shielding ratio over 1:1 for area reduction and compare the aforementioned two structures to coplanar shielding for signal nets. The staggered twisted-bundle has the smallest worst case delay, up to 20% and 5% smaller than the coplanar shielding and twisted bundle, respectively. The staggered twisted bundle also has the smallest worst case noise, up to 6% and 12% less than coplanar shielding and twisted bundle. Furthermore, the staggered twisted bundle has the smallest delay/noise variation between signal nets. We conclude that without increasing routing area, the staggered twisted bundle is better than the twisted bundle and coplanar shielding in terms of performance and noise. This work was presented in ISQED'05 [C66].

References

C66. H. Yu and L. He, "Analysis and Synthesis of Staggered Twisted Bundle for Crosstalk Reduction", International Symposium on Quality Electric Design, pp. 682-687, March 2005. (pdf) (ppt)

C75. J. Chen and L. He, "Transmission Line Modeling and Synthesis for Multi-Channel Communication," IEEE International Behavioral Modeling and Simulation Conference, San Jose, CA, pp. 94-99, September 22-23, 2005. (pdf)

J24. J. Chen and L. He, "Modeling and Synthesis of Multi-Port Lossy Transmission Line for Multi-Channel Interconnect," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pages 1664-1676, Sept. 2006. (pdf)

C92. Changbo Long, Sasank Reddy, Lei He, Sudhakar Pamarti, and Tanay Karnik, "Power-Efficient Pulse Width Modulation DC/DC Converters with Zero Voltage Switching Control", International Symposium on Low Power Electronics and Design, 326-329, Tegernsee, Germany, October 2006. (pdf)

C120. Yiyu Shi, Lei He, and C.-J. Richard Shi,, "Scalable Symbolic Model Order Reduction", IEEE Behaviorial Modeling and Simulation Conference 2008. (pdf)

C121. Yiyu Shi, Jinjun Xiong, Howard Chen, and Lei He,, "Stochastic Current Prediction Enabled Frequency Actuator for Runtime Resonance Noise Reduction", ASPDAC 2009 . (nomination for Best Paper Award). (pdf)

C124. Wei Yao, Yiyu Shi, Lei He and Sudhakar Parmati,,"Worst Case Timing Jitter and Amplitude Noise in Differential Signaling", ISQED 2009 (pdf)

C129. Wei Yao, Yiyu Shi, Lei He and Sudhakar Parmati,,"Joint Design-Time and Post-Silicon Optimization for Digitally Tuned Analog Circuits", ICCAD 2009 (pdf)

C137. Fang Gong, Hao Yu, Yiyu Shi, Daesoo Kim, Junyan Ren, Lei He,, "QuickYield: An Efficient Global-Search Based Parametric Yield Estimation With Performance Constraints", 47th IEEE Design Automation Conference (DAC'10), Anaheim, CA, June 13-18, 2010. (pdf)

C142. Fang Gong, Hao Yu, Lei He, "Stochastic Analog Circuit Behavior Modeling by Point Estimation Method",International Symposium on Physical Design 2011 (ISPD'11), Santa Barbara, California, March 27-30, 2011. (pdf)

C143. Fang Gong, Hao Yu, Lei He, "Fast Non-Monte-Carlo Transient Noise Analysis for High-Precision Analog/RF Circuits by Stochastic Orthogonal Polynomials", 48th IEEE Design Automation Conference (DAC'11), San Diego, CA, June5-10, 2011. (pdf)

C153. Fang Gong, Sina Basir-Kazeruni, Lara Dolecek, Lei He, "A Fast Estimation of SRAM Failure Rate Using Probability Collectives". 2012 International Symposium on Physical Design 2012 (ISPD'12). (pdf)

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