Projects

University of California Los Angeles
EDA Laboratory

Primary investigator (PI)

Design and Design Automation of Mixed-Signal Circuits

Primary investigator (PI)

Prof. Lei He
Prof. Sudhakar Pamarti

Attended students

Hao Yu
Changbo Long
Jun Chen
Yiyu Shi
Xinyi Zhang
Wei Yao

Funding sources
SRC "RINGS: Reconfiguration for Embedded Systems," 2003/9-2007/12

SRC "Crosstalk Insensitive Electrical Signaling for Wired Data Communications," 2008/4 - 2011/3

UC MICRO'06&07 "Circuit Optimization for Robustness and Power Efficiency"

UC MICRO'06&07 "Beyond the die signal integrity"

Research Statement

We design analog circuits for high-speed crosstalk insensitive signaling, field programmable RF interconnect carrying multiple logic channels by one wire, and DC/DC converter. In addition, we also develop behavioral modeling, simulation and design methodology for these analog circuits.

System-in-Package and 3D integration

Variation Aware Modeling and Design

Research Outcomes

Staggered twisted-bundle interconnect for crosstalk and delay reduction. To achieve small delay and low crosstalk for multiple signal nets with capacitive and inductive coupling, we propose in this paper a novel interconnect structure, staggered twisted-bundle wires where groups of twisted wires are staggered. This new structure is different from the previously proposed twisted bundle wires with one group of twisted wires and another group of normal wires. Using accurate circuit models and efficient algorithms to find the worst case noise and delay for comprehensive combinations of signal patterns and a range of arrival times, we assume signal and shielding ratio over 1:1 for area reduction and compare the aforementioned two structures to coplanar shielding for signal nets. The staggered twisted-bundle has the smallest worst case delay, up to 20% and 5% smaller than the coplanar shielding and twisted bundle, respectively. The staggered twisted bundle also has the smallest worst case noise, up to 6% and 12% less than coplanar shielding and twisted bundle. Furthermore, the staggered twisted bundle has the smallest delay/noise variation between signal nets. We conclude that without increasing routing area, the staggered twisted bundle is better than the twisted bundle and coplanar shielding in terms of performance and noise. This work was presented in ISQED'05 [C66].

Transmission line modeling and synthesis for multi channel communication. To overcome the limitations of traditional interconnects, transmission lines that transmit multi-channel signals via high frequency carriers have recently been proposed and realized for intra-chip and inter-chip communication. We derive a closed-form model for SNR for such interconnects with multiple ports and branches, and propose efficient figures of merit (FOMs) to minimize signal distortion. Experiments show that the SNR model is accurate compared to SPICE simulation and signal distortion FOMs are effective. Using the proposed models, we further automatically synthesize coplanar waveguides for radio-frequency (RF) interconnects with capacitive couplers. We minimize the total interconnect area under constraints of SNR and signal distortion. Compared to the published manual designs, the synthesized solution can reduce up to 80% area. Furthermore, the optimized solutions vary greatly with respect to number of ports, frequency bands, topologies and terminations, and therefore automatic synthesis is needed. This work was presented in BMAS'05 [C75] and TCAD [J24].

Power efficient pulse width modulation DC/DC converters with zero voltage switching control. This paper proposes a power-efficient PWM DC/DC converter design with a novel zero voltage switching (ZVS) control technique. The ZVS control is realized by an inner feedback loop which is implemented by simple digital circuitry between the input and output of the power transistors and achieves real-time zero voltage switching (ZVS) for various loading and device parameters with power efficiencies over 90.0%. In addition, an outer feedback loop is used to ensure that the output precisely tracks a reference voltage level. We have also built the relationship between the output voltage ripple and the speed of the voltage comparators which has shown to introduce new low-frequency signals to the loops and cause significant output voltage ripples. Experiment results show that the output ripple could be reduced by 4x by carefully handling the generation and propagation of these low frequency signals. This work was presented in ISLPED'06 [C92]

References

C66. H. Yu and L. He, "Analysis and Synthesis of Staggered Twisted Bundle for Crosstalk Reduction", International Symposium on Quality Electric Design, pp. 682-687, March 2005. (pdf) (ppt)

C75. J. Chen and L. He, "Transmission Line Modeling and Synthesis for Multi-Channel Communication," IEEE International Behavioral Modeling and Simulation Conference, San Jose, CA, pp. 94-99, September 22-23, 2005. (pdf)

J24. J. Chen and L. He, "Modeling and Synthesis of Multi-Port Lossy Transmission Line for Multi-Channel Interconnect," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pages 1664-1676, Sept. 2006. (pdf)

C92. Changbo Long, Sasank Reddy, Lei He, Sudhakar Pamarti, and Tanay Karnik, "Power-Efficient Pulse Width Modulation DC/DC Converters with Zero Voltage Switching Control", International Symposium on Low Power Electronics and Design, 326-329, Tegernsee, Germany, October 2006. (pdf)

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Last update: 01-31-2008.