University of California Los Angeles
Design Automation Laboratory



Layout and Power Estimation and Optimization at Microarchitecture and Register Transfer Levels

Primary Investigator (PI)

  • Prof. Lei He

Attended Students

Funding sources

Intel (2000-2004), SRC project id: 782/1008 (2000-2004)

Research Outcomes

RTL level power estimation: At the Register Transfer Level, the estimation of the maximum current in a power gated circuit must determine the maximum of all possible power-up and normal switching current. We developed a register transfer level leakage estimation considering a rich cell library at ISPD'01 [C20], ASP-DAC'02 [C25], and an IEE journal paper [J20], We proposed a cluster-based ATPG algorithm to estimate the maximum power-up current for combinational circuits. Our method achieved substantial improvement over simulation-based methods and also over the previously proposed ATPG-based methods. Further, we also formulated the sequential circuit maximum current problem as a combinational ATPG problem, and solve it using the cluster-based estimation algorithm. Experimental results showed that the maximum power-up current for sequential circuits can be up to 73% larger than the maximum normal switching current.

Supply voltage and temperature aware performance and power modeling: Both performance and leakage depend on supply voltage and temperature, but such dependency was not carefully modeled at the micro-architecture level. We developed leakage power model with temperature dependence in the context of microprocessors at ISLPED'03 [C35]. We further incorporated such a model into micro-architecture simulation to close the loop between supply voltage, clock rate, power and temperature. We showed that ignoring inter-dependence between them may lead to thermal runaway (i.e., temperature goes to the infinity) or temperature violation in thermal management, and further quantified the benefits of advanced cooling techniques. The results were also presented as an invited paper at DAC'04 [C53] and in TCAD [J17].

Micro-architecture and floorplanning co-optimization: Micro-architecture and floorplanning have been optimized separately under the assumption that interconnects have no pipelining and no impact on system CPI (cycle-per-instruction). Our study in [C38] on interconnect power estimation considering concurrent repeater and flip-flop insertion reduce the over-estimation of whole-chip interconnect power by up to 2.46X, considering microarchitectural level structure interconnects such as global busses. That study further revealed the performance impact of interconnect pipelining. Considering unavoidable interconnect pipelining due to technology scaling, we studied floorplanning optimization to minimize CPI for given micro-architecture configurations. We proposed two algorithms, one based on access ratio without computing CPI and the other based on a trajectory piecewise-linear (TPWL) model to estimate CPI. Compared to the conventional floorplanning to minimize area and wire length, our TPWL-based floorplanning can reduce CPI by up to 72.4% with an area overhead less than 5.0%. Furthermore, we extended the TPWL CPI model to consider micro-architecture changes and developed efficient co-optimization of micro-architecture and floorplanning. Our initial results were published in DAC'04 [C51].


B3. W. Liao and L. He, ``Power Modeling and Reduction of VLIW Processors,'' Compilers and Operating Systems for Low Power , edited by L. Benini, M. Kandemir and J. Ramanujam, ISBN: 1-4020-7573-1, Kluwer Academic Publishers, August 2003, Chapter 9, pp 155-172, (pdf).
J14. W. Liao and L. He, `` Coupled Power and Thermal Simulation with Active Cooling,'' Lecture Notes in Computer Science series, Springer-Verlag Publisher, Volume 3164/2004, pp 148-163, 2004. (pdf)
J17. W. Liao, L. He and K. Lepak, "Temperature and supply voltage aware performance and power modeling at microarchitecture level", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 12 pages, July 2005. (pdf).
J20. F. Li, L. He, J. Basile, R. Patel and H. Ramamurthy, "Leakage Current Aware High-Level Estimation for VLSI circuits", accepted by IEE Proceeding on Computers & Digital Techniques, special issue for 2003 International Workshop on Power and Timing Modeling, Optimization and Simulation. .
C20. F. Li and L. He, "Maximum Current Estimation with Consideration of Power Gating," IEEE/ACM International Symposium on Physical Design, 106-111, April 2001. (pdf)
C22. W. Liao and L. He, "Ongoing Work on Power Modeling and Reduction for VLIW Processors," Workshop on Compilers and Operating Systems for Low Power, September 2001. (pdf)
C25. F. Li and L. He, "Estimation of Maximum Power-up Current," Asia South Pacific Design Automation Conference, January 2002. pp. 51-56 (pdf)
C35. W. Liao, F. Li and L. He, "Microarchitecture Level Power and Thermal Simulation Considering Temperature Dependent Leakage Model," in Proceedings of International Symposium on Low Power Electronics and Design, pages 211-216, August. 2003. (pdf)
C38. W. Liao and L. He, "Full-chip Interconnect Power Estimation and Simulation Considering Concurrent Repeater and Flip-flop Insertion," Proceedings of International Conference on Computer Aided Design, pages: 574-580, November 2003. (pdf)
C39. W. Liao and L. He, "Coupled Power and Thermal Simulation and Its Application", in the 3rd Workshop on Power-Aware Computer Systems, in conjunction with the 36th Annual International Symposium on Microarchitecture, December 2003. (pdf)
C51. C. Long, L. Simonson, W. Liao and L. He, "Floorplanning Optimization with Trajectory Piecewise-Linear Model for Pipelined Interconnects", IEEE/ACM Design Automation Conference, pp. 640-645, June 2004. (pdf)
C53. L. He, W. Liao and M. Stan, "System Level Leakage Reduction Considering Leakage and Thermal Interdependency", IEEE/ACM Design Automation Conference, pp. 12 - 17, June 2004. (pdf) (Invited paper)

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Last update: 10-11-2002