oagFpga::VerilogDesign::Declaration Class Reference

A wire, port, reg, or data type declaration. More...

#include <oagFpgaVerilogDesign.h>

Collaboration diagram for oagFpga::VerilogDesign::Declaration:

[legend]List of all members.

Public Types
enum	Type {   UNKNOWN, INPUT, OUTPUT, WIRE,   REG, INOUT, PARAMETER, SUPPLY0,   SUPPLY1, TRI, WIREAND, WIREOR,   TRI0, TRI1, TRIAND, TRIOR }
Public Member Functions
	Declaration ()
	~Declaration ()
	Destructor.
Public Attributes
std::string	name
Type	type
Expression *	start
Expression *	stop
Expression *	start2D
Expression *	stop2D
Expression *	value

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Detailed Description

A wire, port, reg, or data type declaration.

Five declaration types are currently supported:

• wire
• input, output, inout
• reg

Definition at line 95 of file oagFpgaVerilogDesign.h.

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Member Enumeration Documentation

enum oagFpga::VerilogDesign::Declaration::Type

Enumeration values: UNKNOWN  INPUT  OUTPUT  WIRE  REG  INOUT  PARAMETER  SUPPLY0  SUPPLY1  TRI  WIREAND  WIREOR  TRI0  TRI1  TRIAND  TRIOR  Definition at line 99 of file oagFpgaVerilogDesign.h.

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Constructor & Destructor Documentation

oagFpga::VerilogDesign::Declaration::Declaration (   )  [inline]

Definition at line 123 of file oagFpgaVerilogDesign.h.

oagFpga::VerilogDesign::Declaration::~Declaration (   )

Destructor. Definition at line 86 of file oagFpgaVerilogDesign.cpp. References start, start2D, and stop.

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Member Data Documentation

std::string oagFpga::VerilogDesign::Declaration::name

Definition at line 98 of file oagFpgaVerilogDesign.h. Referenced by oagFpga::VerilogSynthesis::synthesizeBlock(), oagFpga::VerilogSynthesis::synthesizeModuleNets(), and oagFpga::VerilogSynthesis::synthesizeModuleTerms().

Expression* oagFpga::VerilogDesign::Declaration::start

Definition at line 118 of file oagFpgaVerilogDesign.h. Referenced by oagFpga::VerilogSynthesis::synthesizeBlock(), oagFpga::VerilogSynthesis::synthesizeModuleNets(), and ~Declaration().

Expression* oagFpga::VerilogDesign::Declaration::start2D

Definition at line 119 of file oagFpgaVerilogDesign.h. Referenced by oagFpga::VerilogSynthesis::synthesizeBlock(), oagFpga::VerilogSynthesis::synthesizeModuleNets(), and ~Declaration().

Expression * oagFpga::VerilogDesign::Declaration::stop

Definition at line 118 of file oagFpgaVerilogDesign.h. Referenced by oagFpga::VerilogSynthesis::synthesizeBlock(), oagFpga::VerilogSynthesis::synthesizeModuleNets(), and ~Declaration().

Expression * oagFpga::VerilogDesign::Declaration::stop2D

Definition at line 119 of file oagFpgaVerilogDesign.h. Referenced by oagFpga::VerilogSynthesis::synthesizeBlock(), and oagFpga::VerilogSynthesis::synthesizeModuleNets().

Type oagFpga::VerilogDesign::Declaration::type

Definition at line 116 of file oagFpgaVerilogDesign.h. Referenced by oagFpga::VerilogSynthesis::synthesizeBlock(), oagFpga::VerilogSynthesis::synthesizeModuleNets(), and oagFpga::VerilogSynthesis::synthesizeModuleTerms().

Expression* oagFpga::VerilogDesign::Declaration::value

Definition at line 121 of file oagFpgaVerilogDesign.h.

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The documentation for this class was generated from the following files:

• oagFpgaVerilogDesign.h
• oagFpgaVerilogDesign.cpp

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