oagFpga::VerilogDesign::PortConnection Class Reference

A port connection inside of a module instantiation. More...

#include <oagFpgaVerilogDesign.h>

Collaboration diagram for oagFpga::VerilogDesign::PortConnection:

[legend]List of all members.

Public Member Functions
	PortConnection ()
	PortConnection (const std::string &n, int p, Expression *v)
	~PortConnection ()
	Destructor.
Public Attributes
std::string	name
int	position
Expression *	value

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Detailed Description

A port connection inside of a module instantiation.

Definition at line 344 of file oagFpgaVerilogDesign.h.

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Constructor & Destructor Documentation

oagFpga::VerilogDesign::PortConnection::PortConnection (   )  [inline]

Definition at line 351 of file oagFpgaVerilogDesign.h.

oagFpga::VerilogDesign::PortConnection::PortConnection (  const std::string &  n, int  p, Expression *  v )  [inline]

Definition at line 352 of file oagFpgaVerilogDesign.h.

oagFpga::VerilogDesign::PortConnection::~PortConnection (   )

Destructor. Definition at line 250 of file oagFpgaVerilogDesign.cpp.

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Member Data Documentation

std::string oagFpga::VerilogDesign::PortConnection::name

Definition at line 347 of file oagFpgaVerilogDesign.h. Referenced by oagFpga::VerilogSynthesis::synthesizeModuleInsts().

int oagFpga::VerilogDesign::PortConnection::position

Definition at line 348 of file oagFpgaVerilogDesign.h. Referenced by oagFpga::VerilogSynthesis::synthesizeModuleInsts().

Expression* oagFpga::VerilogDesign::PortConnection::value

Definition at line 349 of file oagFpgaVerilogDesign.h. Referenced by oagFpga::VerilogSynthesis::synthesizeModuleInsts().

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The documentation for this class was generated from the following files:

• oagFpgaVerilogDesign.h
• oagFpgaVerilogDesign.cpp

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