oagFpgaDebug.h File Reference

#include <iostream>

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Defines
#define	DEBUG   1
#define	QUIT_ON_ERROR
#define	QUIT_ON_INTERNAL_ERROR
#define	DEBUG_SYMBOL   '>'
#define	DEBUG_PRINT(x)   { cerr << DEBUG_SYMBOL << " " << x; }
#define	DEBUG_PRINTLN(x)   { cerr << DEBUG_SYMBOL << " " << x << endl; }
#define	DEBUG_PRINTMORE(x)   { cerr << x; }
#define	YU_TEST   1

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Define Documentation

#define DEBUG   1

Definition at line 6 of file oagFpgaDebug.h.

#define DEBUG_PRINT (  x   )     { cerr << DEBUG_SYMBOL << " " << x; }

Definition at line 28 of file oagFpgaDebug.h. Referenced by oagFpga::ModGraph::findDriverOfEquivalentNets(), oagFpga::AiModGraph::findDriverOfEquivalentNets(), oagFunc::SimOcc::runFull(), oagFpga::SimMod::runOne(), oagFpga::VerilogSynthesis::synthesizeBlock(), and oagFpga::VerilogSynthesis::synthesizeModuleNets().

#define DEBUG_PRINTLN (  x   )     { cerr << DEBUG_SYMBOL << " " << x << endl; }

Definition at line 29 of file oagFpgaDebug.h. Referenced by oagFpga::ModuleCompiler::annotateAsynchronousSignal(), oagFpga::Synthesis::assignMultiRef(), oagFpga::ModuleCompiler::BBRef2AiRef(), oagFpga::Synthesis::binaryBusInputOutputOpt(), oagFpga::Manager::create(), oagFpga::Synthesis::createBusNet(), oagFpga::Synthesis::createModule(), oagFpga::VerilogSynthesis::evaluateConstantExpression(), oagFpga::VerilogSynthesis::evaluateExpression(), oagFpga::VerilogSynthesis::evaluateLval(), oagFpga::Synthesis::findModule(), oagFpga::OccGraph::getAllConnections(), oagFpga::RtlGraph::hasCombinationalCycle(), oagFpga::MapperUtils::identifyControls(), oagFpga::RtlGraph::newTerminal(), oagFpga::Observer::Observer(), oagFpga::Observer::onFirstOpen(), oagFpga::Observer::onPostSave(), oagFpga::Observer::onPreSave(), oagFpga::Observer::onPurge(), oagFpga::MapperUtils::removeDanglingNets(), oagFpga::Synthesis::seq(), oagFpga::ModuleCompiler::seq(), oagFpga::Manager::serialize(), oagFpga::Manager::setNetToBBConnection(), oagFpga::VerilogSynthesis::synthesizeBlock(), oagFpga::VerilogSynthesis::synthesizeBlockingassignment(), oagFpga::VerilogSynthesis::synthesizeCase(), oagFpga::VerilogSynthesis::synthesizeCaseEasy(), oagFpga::VerilogSynthesis::synthesizeIf(), oagFpga::VerilogSynthesis::synthesizeModule(), oagFpga::VerilogSynthesis::synthesizeModuleAssigns(), oagFpga::VerilogSynthesis::synthesizeModuleFunc(), oagFpga::VerilogSynthesis::synthesizeModuleInsts(), oagFpga::VerilogSynthesis::synthesizeModuleNets(), oagFpga::VerilogSynthesis::synthesizeModuleTerms(), oagFpga::VerilogSynthesis::synthesizeNonblockingassignment(), and oagFpga::Manager::unserialize().

#define DEBUG_PRINTMORE (  x   )     { cerr << x; }

Definition at line 30 of file oagFpgaDebug.h. Referenced by oagFpga::ModGraph::findDriverOfEquivalentNets(), oagFpga::AiModGraph::findDriverOfEquivalentNets(), oagFunc::SimOcc::runFull(), oagFpga::SimMod::runOne(), oagFpga::VerilogSynthesis::synthesizeBlock(), and oagFpga::VerilogSynthesis::synthesizeModuleNets().

#define DEBUG_SYMBOL   '>'

Definition at line 24 of file oagFpgaDebug.h.

#define QUIT_ON_ERROR

Value: { \ assert(false); \ exit(0); } Definition at line 8 of file oagFpgaDebug.h. Referenced by oagFpga::OccGraph::getTerminalDriver().

#define QUIT_ON_INTERNAL_ERROR

Value: { \ assert(false); \ cerr << "ERROR: Internal error" << endl; \ exit(0); } Definition at line 11 of file oagFpgaDebug.h. Referenced by oagFpga::VerilogSynthesis::synthesizeModuleInsts().

#define YU_TEST   1

Definition at line 37 of file oagFpgaDebug.h.

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