oagFpgaManager.cpp

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#include "oagFpga.h"
#include "oagFpgaManager.h"
#include "oagAiGraph.h"
#include <list>
#include <map>
#include <assert.h>
#include <iostream>

#include "oagFpgaDebug.h"

namespace oagFpga {
 

// *****************************************************************************
// Class static variable definitions.
// *****************************************************************************

#if defined(CACHE_LAST_MANAGER_LOOKUP)
  oa::oaDesign *Manager::lastManagerDesign;
  Manager      *Manager::lastManagerObject;
#endif


// *****************************************************************************
// Manager() constructor
//
// *****************************************************************************
Manager::Manager(oa::oaDesign *design) {

    // does this design already have a Manager associated with it?
    if(hasManager(design)) {
        cerr << "ERROR: Manager for design already exists" << endl;
        QUIT_ON_ERROR;
    }
    
    // initialize variables and caches
    this->design = design;
    //preflattenedCache.clear();

    // associate this manager with the design by setting an AppDef
    managerAppDef->set(design, this);
    
    // design must have a top module
    oa::oaModule *module;
    if (!(module = design->getTopModule())) {
        module = oa::oaModule::create(design);
        design->setTopModule(module);
    }
     
}
 

// *****************************************************************************
// create()
//
//
// *****************************************************************************
Manager *
Manager::create(oa::oaDesign *design) {

    if (hasManager(design)) {
        return static_cast<Manager*>(managerAppDef->get(design));
    }

    // there is no Manager yet associated with this design
    Manager *manager = new Manager(design);

    // create a terminal BB node for each net in each module
    oa::oaModule *module;
    oa::oaIter<oa::oaModule> modIter(design->getModules());
    while((module = modIter.getNext())) { 
        oa::oaModBitNet *net;
        oa::oaIter<oa::oaModBitNet> netIter(module->getNets(oacNetIterAll));
        while((net = netIter.getNext())) {
            if(net->getNumBits() > 1) {
                // YH: I don't understand why we don't create terminal BB for
                // multiBit-net
                // Guess: in oa::oaModBusNet::create routine, it will automatically 
                // create multiple scalarNet in the same time when a bus net is created.
#ifdef DEBUG
                oa::oaString str;
                net->getName(oa::oaVerilogNS(), str);
                DEBUG_PRINTLN("In create manager, busnet: " << str);
#endif
                continue;
            }
#ifdef DEBUG
                oa::oaString str;
                net->getName(oa::oaVerilogNS(), str);
                DEBUG_PRINTLN("In create manager, scalar net: " << str);
#endif

            // clear an existing AppDef, if it exists
            bbRefAppDef->destroy(net);
            AiRefAppDef->destroy(net);

            // create a terminal to connect the net to the RTL graph
            manager->prepareNetToBBConnection(net);

            // create a terminal to connect the net to the AI graph
            manager->prepareNetToAiConnection(net);
        }

        // tie the 0 and 1 nets appropriately
        oa::oaNativeNS      nativeNS;
        oa::oaModScalarNet *logicConstantNet;
        logicConstantNet = oa::oaModScalarNet::find(module, oa::oaScalarName(nativeNS, "tie0"));

        if (logicConstantNet) {
            manager->bbg.setTerminalDriver(bbRefAppDef->get(logicConstantNet),
                    manager->bbg.constantZero());
            manager->ai.setTerminalDriver(AiRefAppDef->get(logicConstantNet), 
                manager->ai.constantZero());
        }

        logicConstantNet = oa::oaModScalarNet::find(module, oa::oaScalarName(nativeNS, "tie1"));

        if (logicConstantNet) {
            manager->bbg.setTerminalDriver(bbRefAppDef->get(logicConstantNet),
                    manager->bbg.constantOne());
            manager->ai.setTerminalDriver(AiRefAppDef->get(logicConstantNet), 
                manager->ai.constantOne());
        }
    }

    return manager;
}


// *****************************************************************************
// destory()
//
//
// *****************************************************************************
void
Manager::destroy(oa::oaDesign *design) {
  // is there a Manager?
  if (!hasManager(design)) {
    return;
  }
    
  // remove links from nets to AI graph
  oa::oaModule *module;
  oa::oaIter<oa::oaModule> modIter(design->getModules());
  while((module = modIter.getNext())) {   
    oa::oaModBitNet *net;
    oa::oaIter<oa::oaModBitNet> netIter(module->getNets(oacNetIterAll));
    while((net = netIter.getNext())) {
      if(net->getNumBits() > 1) {
        continue;
      }
      
      // clear an existing AppDef, if it exists
      bbRefAppDef->destroy(net);
      AiRefAppDef->destroy(net);
    }
  }
  
  // delete manager object
  delete static_cast<Manager*>(managerAppDef->get(design));
  managerAppDef->destroy(design);
}


// *****************************************************************************
// ~Manager() destructor
//
// *****************************************************************************
Manager::~Manager() {
}


// *****************************************************************************
// prepareNetToBBConnection()
//
//
// *****************************************************************************
BBRef
Manager::prepareNetToBBConnection(oa::oaModBitNet *net) {
    assert(net);
    
    // is there already an terminal node associated with this net?
    if (net->getAppDefs().includes(bbRefAppDef)) {
        BBRef terminal = bbRefAppDef->get(net);  
        assert(bbg.isTerminal(terminal));
        return terminal;
    }

    // create a new terminal node
    BBRef terminal = bbg.newTerminal(bbg.getNull());
    //bbg.incrementExternalReferences(terminal);
    setNetToBBConnection(net, terminal);
    return terminal;
}

// *****************************************************************************
// prepareNetToAiConnection()
//
//
// *****************************************************************************
BBRef
Manager::prepareNetToAiConnection(oa::oaModBitNet *net) {
    assert(net);
    
    // is there already an terminal node associated with this net?
    if (net->getAppDefs().includes(AiRefAppDef)) {
        oagAi::Ref terminal = AiRefAppDef->get(net);  
        assert(ai.isTerminal(terminal));
        return terminal;
    }

    // create a new terminal node
    oagAi::Ref terminal = ai.newTerminal(ai.getNull());
    //bbg.incrementExternalReferences(terminal);
    setNetToAiConnection(net, terminal);
    return terminal;
}

// *****************************************************************************
// getSerializedSize()
//
//
// *****************************************************************************
int         
Manager::getSerializedSize(oa::oaDesign *design) {
    assert(design);
    
    // YH: getSerializedSize() need to be rewrite

/*
    if (!Manager::hasManager(design)) {
        return 0;
    }

    Manager *manager = Manager::get(design);

    int bytes = 0;
    
    long numNodes = manager->ai.getNumNodes() - manager->ai.NODES_TO_IGNORE;
    bytes += sizeof(numNodes);

    while(--numNodes >= 0) {
        oagAi::Node *node = manager->ai.getNode((numNodes+manager->ai.NODES_TO_IGNORE)*2);
        bytes += node->getSerializedSize();
    }
    
    return bytes;
*/
}


// *****************************************************************************
// serialize()
//
//
// *****************************************************************************
void         
Manager::serialize(void* buf, oa::oaDesign *design) {
    assert(buf);
    assert(design);
    assert(design->getTopModule());
    
    oa::oaString moduleNameString;
    design->getTopModule()->getName(oa::oaVerilogNS(), moduleNameString);
    DEBUG_PRINTLN("serializing " << moduleNameString)
    
    // is there any functional information to serialize?
    if (!Manager::hasManager(design)) {
        return;
    }
    
    Manager *manager = Manager::get(design);
    
    void *ptr = buf;
    
    // YH: serialize() need to be rewrite

    /*
    long numNodes = manager->ai.getNumNodes() - manager->ai.NODES_TO_IGNORE;
    memcpy(ptr, &numNodes, sizeof(numNodes));
    char *char_ptr = static_cast<char*>(ptr);
    char_ptr += sizeof(numNodes);
    ptr = char_ptr;
    DEBUG_PRINTLN("\twriting " << numNodes << " AI nodes")
    
    oagAi::Ref currentRef = manager->ai.NODES_TO_IGNORE*2;
    while(--numNodes >= 0) {
        oagAi::Node *node = manager->ai.getNode(currentRef);
        node->serialize(ptr);
        char *char_ptr = static_cast<char*>(ptr);
        char_ptr += node->getSerializedSize();
        ptr = char_ptr;
        currentRef += 2;
    }

*/
#ifdef DEBUG
    long bytes = reinterpret_cast<long>(ptr)-reinterpret_cast<long>(buf);
    DEBUG_PRINTLN("\twrote " << bytes << " bytes");
#endif
}


// *****************************************************************************
// unserialize()
//
//
// *****************************************************************************
int
Manager::unserialize(void *buf, oa::oaDesign *design) {
    assert(design);
    assert(design->getTopModule());
    
    oa::oaString moduleNameString;
    design->getTopModule()->getName(oa::oaVerilogNS(), moduleNameString);
    DEBUG_PRINTLN("unserializing " << moduleNameString)

    if (Manager::hasManager(design)) {
        QUIT_ON_INTERNAL_ERROR;
    }
    Manager *manager = new Manager(design);
    void *ptr = buf;
    
    // YH: unserialize() need to be rewrite
    
    /*
    long numNodes;
    memcpy(&numNodes, ptr, sizeof(numNodes));
    char *char_ptr = static_cast<char*>(ptr);
    char_ptr += sizeof(numNodes);    
    ptr = char_ptr;
    DEBUG_PRINTLN("\treading " << numNodes << " AI nodes")

    // recreate all nodes
    assert(manager->ai.getNumNodes() == manager->ai.NODES_TO_IGNORE);
    while(--numNodes >= 0) {
        oagAi::Node *node = manager->ai.newNode();
        char *char_ptr = static_cast<char*>(ptr);
        char_ptr += node->unserialize(ptr);
        ptr = char_ptr;
    }
    // rebuild all non-persistent data
    oagAi::Ref currentRef = manager->ai.NODES_TO_IGNORE*2;
    oagAi::Ref lastRef = (manager->ai.getNumNodes()-1)*2;
    while(currentRef <= lastRef) {
        switch(manager->ai.getNodeType(currentRef)) {
          case oagAi::Node::TERMINAL: {
            // update fan-outs and reference counts
            manager->ai.addToFanout(manager->ai.getTerminalDriver(currentRef), currentRef);
            break;
            }
          case oagAi::Node::SEQUENTIAL: {
            // update fan-outs and reference counts
            manager->ai.addToFanout(manager->ai.getNextState(currentRef), currentRef);
            manager->ai.seqNodes++;
            break;
            }
          case oagAi::Node::AND: {
            // update fan-outs and reference counts          
            manager->ai.addToFanout(manager->ai.getAndLeft(currentRef), currentRef);
            manager->ai.addToFanout(manager->ai.getAndRight(currentRef), currentRef);            
    
            // add node to structural hash table
            int hash_key = manager->ai.getStructuralHashKey(manager->ai.getAndLeft(currentRef),manager->ai.getAndLeft(currentRef));
            manager->ai.getNode(currentRef)->next = manager->ai.structuralHash[hash_key];
            manager->ai.structuralHash[hash_key] = currentRef;

            manager->ai.andNodes++;
            break; 
            }
          default:
            break;
        }
        currentRef += 2;
    }

    DEBUG_PRINTLN("\t\tfinal num nodes =  " << manager->ai.getNumNodes())
    DEBUG_PRINTLN("\t\t\tlastPage = " << manager->ai.lastPage << " lastIndex = " << manager->ai.lastIndex)

    // 1. increment refcounts of nodes that are attached to nets
    // 2. set external_terminal_connection pointers to nets

    oa::oaModule *module;
    oa::oaIter<oa::oaModule> modIter(design->getModules());
    while((module = modIter.getNext())) {      
        oa::oaModNet *net;
        oa::oaIter<oa::oaModNet> netIter(module->getNets(oacNetIterSingleBit));
        while((net = netIter.getNext())) {
            oa::oaModBitNet *bit = toBitNet(net);
            if (!manager->ai.isNull(currentRef = manager->getNetToAiConnection(bit))) {
                manager->ai.incrementExternalReferences(currentRef);
                manager->ai.setExternalTerminalConnection(currentRef, reinterpret_cast<void *>(bit));
            }
        }
    }
    */
    
    long bytes = reinterpret_cast<long>(ptr)-reinterpret_cast<long>(buf);
    DEBUG_PRINTLN("\tread " << bytes << " bytes");
    return bytes;
}

// *****************************************************************************
// removeNetToAiConnection()
//
//
// *****************************************************************************
void
Manager::removeNetToAiConnection(oa::oaModBitNet *net) {
    assert(net);

    // remove the pointer from the node to the net    
    if (net->getAppDefs().includes(AiRefAppDef)) {
        oagAi::Ref ref = AiRefAppDef->get(net);
        assert(!ai.isNull(ref));
        ai.setExternalTerminalConnection(ref, NULL);    
    }
    
    // remove the pointer from the net to the node
    AiRefAppDef->destroy(net);
}

// *****************************************************************************
// setNetToBBConnection()
//
//
// *****************************************************************************
// YH: 05/09/2007, TODO update this routine to black box port
// YH: 05/10/2007, DONE!
void
Manager::setNetToBBConnection(oa::oaModBitNet *net, BBRef bbRef) {

    if(bbg.getNodeType(bbRef) != RtlNode::TERMINAL) {
        cerr << "ERROR: Nets can only be connected to TERMINAL nodes:";
        QUIT_ON_ERROR;
    } 

#ifdef DEBUG
    oa::oaString str;
    net->getName(oa::oaVerilogNS(), str);
    DEBUG_PRINTLN("setNetToBBConnection: " << str);
#endif

    bbRefAppDef->set(net, bbRef);
    bbg.setExternalTerminalConnection(bbRef, reinterpret_cast<void*>(net));
}

// *****************************************************************************
// setNetToAiConnection()
//
//
// *****************************************************************************
void
Manager::setNetToAiConnection(oa::oaModBitNet *net, oagAi::Ref ref) {
    if(ai.getNodeType(ref) != oagAi::Node::TERMINAL) {
        cerr << "ERROR: Nets can only be connected to TERMINAL nodes:";
        ai.print(ref);
        QUIT_ON_ERROR;
    } else if (ai.isInverted(ref)) {
        cerr << "ERROR: Nets can only be connected to non-inverted references: ";
        ai.print(ref);
        QUIT_ON_ERROR;
    }

    oa::oaString str;
    net->getName(oa::oaVerilogNS(), str);
    AiRefAppDef->set(net, ref);
    ai.setExternalTerminalConnection(ref, reinterpret_cast<void*>(net));
}


// *****************************************************************************
// getNetToBBConnection()
//
//
// *****************************************************************************
oa::oaModBitNet *
Manager::getNetToBBConnection(BBRef ref) {
    assert(bbg.getNodeType(ref) == RtlNode::TERMINAL);

    // is the pointer to the connected net stored in the terminal node?
    void *external_terminal_connection = bbg.getExternalTerminalConnection(ref);
    oa::oaModBitNet *bit;
    if (external_terminal_connection) {
        bit = reinterpret_cast<oa::oaModBitNet*>(external_terminal_connection);
        assert(getNetToBBConnection(bit) == ref);
        return bit;
    }
    
    return NULL;
}

// *****************************************************************************
// getNetToAiConnection()
//
//
// *****************************************************************************
oa::oaModBitNet *
Manager::getNetToAiConnection(oagAi::Ref ref) {
    assert(ai.getNodeType(ref) == oagAi::Node::TERMINAL);

    // is the pointer to the connected net stored in the terminal node?
    void *external_terminal_connection = ai.getExternalTerminalConnection(ref);
    oa::oaModBitNet *bit;
    if (external_terminal_connection) {
        bit = reinterpret_cast<oa::oaModBitNet*>(external_terminal_connection);
        assert(getNetToAiConnection(bit) == ref);
        return bit;
    }
    
    return NULL;
}

// *****************************************************************************
// isStructural()
//
//
// *****************************************************************************
bool
Manager::isStructural() {
    assert(design);
    assert(design->getTopModule());

    // if there are any black box nodes in the graph, the design
    // is not structural
    if (bbg.getBBNodeNum() > 0) {
        return false;
    }

    return true;
}

// *****************************************************************************
// getNetToBBConnection()
//
//
// *****************************************************************************
BBRef
Manager::getNetToBBConnection(oa::oaModBitNet *net) {

    BBRef ref = bbg.getNull();
    
    // examine each one of the functionally equivalent nets
    if (net->getAppDefs().includes(bbRefAppDef)) {
        ref = bbRefAppDef->get(net);
        assert(!bbg.isNull(ref));
        assert(bbg.isTerminal(ref));
        return ref;
    }
    
    return bbg.getNull();

}

// *****************************************************************************
// getNetToAiConnection()
//
//
// *****************************************************************************
oagAi::Ref
Manager::getNetToAiConnection(oa::oaModBitNet *net) {

    oagAi::Ref ref = ai.getNull();
    
    // examine each one of the functionally equivalent nets
    if (net->getAppDefs().includes(AiRefAppDef)) {
        ref = AiRefAppDef->get(net);
        assert(!ai.isNull(ref));
        assert(ai.isTerminal(ref));
        return ref;
    }
    
    return ai.getNull();

}

/*

// *****************************************************************************
// getLocalAIsize()
//
//
// *****************************************************************************
int
Manager::getLocalAIsize() {
    return ai.getNumNodes();
}


// *****************************************************************************
// getHierarchicalAIsize()
//
//
// *****************************************************************************
int
Manager::getHierarchicalAIsize() {
    assert(design);
    
    return getHierarchicalAIsize(design);
}


// *****************************************************************************
// getHierarchicalAIsize()
//
//
// *****************************************************************************
int
Manager::getHierarchicalAIsize(oa::oaDesign *design) {
    assert(design);
    assert(design->getTopOccurrence());

    int num = 0;
    
    // if this design is not entirely structural, add the number of nodes here
    if (Manager::hasManager(design)) {
        num += Manager::get(design)->ai.getNumNodes();
    }
    
    // traverse the ModuleInst hierarchy, and recurse on any DesignInsts
    list<oa::oaModule*> toBeVisited;
    toBeVisited.push_back(design->getTopModule());
 
    while(!toBeVisited.empty()) {
        oa::oaModule *module = toBeVisited.front();
        toBeVisited.pop_front();

        oa::oaModInst *inst;
        oa::oaIter<oa::oaModInst> instIter(module->getInsts());
        while((inst = instIter.getNext())) {
            assert(inst);

            oa::oaModule *subMod = inst->getMasterModule();
            if (!subMod) {
              assert(inst->isModDesignInst());
              oa::oaModDesignInst *designInst = static_cast<oa::oaModDesignInst *>(inst);
              oa::oaString libNameString, cellNameString, viewNameString;
              designInst->getLibName(oa::oaNativeNS(), libNameString);
              designInst->getCellName(oa::oaNativeNS(), cellNameString);
              designInst->getViewName(oa::oaNativeNS(), viewNameString);
              cerr << "ERROR: Can not bind to " << libNameString << "/" << cellNameString << "/" << viewNameString << endl;
              QUIT_ON_ERROR;
            }

            if (inst->isModDesignInst()) {
                num += getHierarchicalAIsize(subMod->getDesign());
            } else if (inst->isModModuleInst()) {
                toBeVisited.push_front(subMod);
            } else {
                QUIT_ON_INTERNAL_ERROR;
            }
        }
    }
      
    return num;
}


// *****************************************************************************
// getLocalAndAIsize()
//
//
// *****************************************************************************
int
Manager::getLocalAndAIsize() {
    return ai.getNumAndNodes();
}


// *****************************************************************************
// getHierarchicalAndAIsize()
//
//
// *****************************************************************************
int
Manager::getHierarchicalAndAIsize() {
    assert(design);
    
    return getHierarchicalAndAIsize(design);
}


// *****************************************************************************
// getHierarchicalAndAIsize()
//
//
// *****************************************************************************
int
Manager::getHierarchicalAndAIsize(oa::oaDesign *design) {
    assert(design);
    assert(design->getTopOccurrence());

    int num = 0;
    
    // if this design is not entirely structural, add the number of AND nodes here
    if (Manager::hasManager(design)) {
        num += Manager::get(design)->ai.getNumAndNodes();
    }
    
    // traverse the ModuleInst hierarchy, and recurse on any DesignInsts
    list<oa::oaModule*> toBeVisited;
    toBeVisited.push_back(design->getTopModule());
 
    while(!toBeVisited.empty()) {
        oa::oaModule *module = toBeVisited.front();
        toBeVisited.pop_front();

        oa::oaModInst *inst;
        oa::oaIter<oa::oaModInst> instIter(module->getInsts());
        while((inst = instIter.getNext())) {
            assert(inst);

            oa::oaModule *subMod = inst->getMasterModule();
            if (!subMod) {
              assert(inst->isModDesignInst());
              oa::oaModDesignInst *designInst = static_cast<oa::oaModDesignInst *>(inst);
              oa::oaString libNameString, cellNameString, viewNameString;
              designInst->getLibName(oa::oaNativeNS(), libNameString);
              designInst->getCellName(oa::oaNativeNS(), cellNameString);
              designInst->getViewName(oa::oaNativeNS(), viewNameString);
              cerr << "ERROR: Can not bind to " << libNameString << "/" << cellNameString << "/" << viewNameString << endl;
              QUIT_ON_ERROR;
            }

            if (inst->isModDesignInst()) {
                num += getHierarchicalAndAIsize(subMod->getDesign());
            } else if (inst->isModModuleInst()) {
                toBeVisited.push_front(subMod);
            } else {
                QUIT_ON_INTERNAL_ERROR;
            }
        }
    }
      
    return num;
}

// *****************************************************************************
// getLocalSeqNodeCount()
//
//
// *****************************************************************************
int
Manager::getLocalSeqNodeCount() {
    return ai.getNumSeqNodes();
}


// *****************************************************************************
// getHierarchicalSeqNodeCount()
//
//
// *****************************************************************************
int
Manager::getHierarchicalSeqNodeCount() {
    assert(design);
    
    return getHierarchicalSeqNodeCount(design);
}


// *****************************************************************************
// getHierarchicalSeqNodeCount
//
//
// *****************************************************************************
int
Manager::getHierarchicalSeqNodeCount(oa::oaDesign *design) {
    assert(design);
    assert(design->getTopOccurrence());

    int num = 0;
    
    // if this design is not entirely structural, add the number of AND nodes here
    if (Manager::hasManager(design)) {
        num += Manager::get(design)->ai.getNumSeqNodes();
    }
    
    // traverse the ModuleInst hierarchy, and recurse on any DesignInsts
    list<oa::oaModule*> toBeVisited;
    toBeVisited.push_back(design->getTopModule());
 
    while(!toBeVisited.empty()) {
        oa::oaModule *module = toBeVisited.front();
        toBeVisited.pop_front();

        oa::oaModInst *inst;
        oa::oaIter<oa::oaModInst> instIter(module->getInsts());
        while((inst = instIter.getNext())) {
            assert(inst);

            oa::oaModule *subMod = inst->getMasterModule();
            if (!subMod) {
              assert(inst->isModDesignInst());
              oa::oaModDesignInst *designInst = static_cast<oa::oaModDesignInst *>(inst);
              oa::oaString libNameString, cellNameString, viewNameString;
              designInst->getLibName(oa::oaNativeNS(), libNameString);
              designInst->getCellName(oa::oaNativeNS(), cellNameString);
              designInst->getViewName(oa::oaNativeNS(), viewNameString);
              cerr << "ERROR: Can not bind to " << libNameString << "/" << cellNameString << "/" << viewNameString << endl;
              QUIT_ON_ERROR;
            }

            if (inst->isModDesignInst()) {
                num += getHierarchicalSeqNodeCount(subMod->getDesign());
            } else if (inst->isModModuleInst()) {
                toBeVisited.push_front(subMod);
            } else {
                QUIT_ON_INTERNAL_ERROR;
            }
        }
    }
      
    return num;
}


// *****************************************************************************
// getNumTotalInstances()
//
//
// *****************************************************************************
int
Manager::getNumTotalInstances() {
    assert(design);
    
    return getNumTotalInstances(design) + 1;
}


// *****************************************************************************
// getNumTotalInstances()
//
//
// *****************************************************************************
int
Manager::getNumTotalInstances(oa::oaDesign *design) {
    assert(design);
    assert(design->getTopOccurrence());
    
    int num = 0;
    
    // add the number of instances inside this instance
    num += design->getTopOccurrence()->getInsts().getCount();
    
    // add the number of instances inside each instance
    oa::oaOccInst *inst;
    oa::oaIter<oa::oaOccInst> instIter(design->getTopOccurrence()->getInsts());
    while((inst = instIter.getNext())) {
        assert(inst->getMasterOccurrence());
        assert(inst->getMasterOccurrence()->getModule());
        num += getNumTotalInstances(inst->getMasterOccurrence()->getModule()->getDesign());
    }

    return num;
}


// *****************************************************************************
// getNumLeafInstances()
//
//
// *****************************************************************************
int
Manager::getNumLeafInstances() {
    assert(design);
    
    return getNumLeafInstances(design);
}


// *****************************************************************************
// getNumLeafInstances()
//
//
// *****************************************************************************
int
Manager::getNumLeafInstances(oa::oaDesign *design) {
    assert(design);
    assert(design->getTopOccurrence());
    
    int num = 0;
    
    // add the number of leaves in each instance
    oa::oaOccInst *inst;
    oa::oaIter<oa::oaOccInst> instIter(design->getTopOccurrence()->getInsts());
    while((inst = instIter.getNext())) {
        assert(inst->getMasterOccurrence());
        assert(inst->getMasterOccurrence()->getModule());    
        num += getNumLeafInstances(inst->getMasterOccurrence()->getModule()->getDesign());
    }
    
    if (num != 0) {
        // non-leaf
        return num;
    } else {
        // leaf
        return 1;    
    }
}

*/


// *****************************************************************************
// print()
//
//
// *****************************************************************************


void
Manager::print(ostream& os) {

    const oa::oaVerilogNS verilogNS;
   
    oa::oaModule *module; 
    oa::oaIter<oa::oaModule> modIter(design->getModules());
    while((module = modIter.getNext())) {
        
        oa::oaModNet *net;
        oa::oaIter<oa::oaModNet> netIter(module->getNets(oacNetIterSingleBit));
        while((net = netIter.getNext())) {
            oa::oaString netNameString;
            net->getName(verilogNS, netNameString);

            BBRef ref = getNetToBBConnection(toBitNet(net));
            if (!bbg.isNull(ref)) {
                os << "net \"" << netNameString << "\" -> " << ref << endl;
            } else {
                os << "net \"" << netNameString << "\" is not connected to a graph node" << endl;
            }
        }
    }

    bbg.print(os);
}

}

---