oagFpgaSynthesis.cpp

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#include "oaDesignDB.h"
#include "oagFpgaManager.h"
#include "oagFpgaSynthesis.h"
#include <list>
#include <set>

//#define DEBUG

#include "oagFpgaDebug.h"

#define sign(a)  ( (a)==0?0: ((a)<0?-1:1) )
#define abs(a)   ( (a)>=0?(a):-(a) )
#define max(a,b) ( (a)>(b)?(a):(b) )
#define min(a,b) ( (a)>(b)?(b):(a) )

namespace oagFpga {

// *****************************************************************************
// Class static variable definitions.
// *****************************************************************************

oa::oaNameSpace                     *Synthesis::nameSpace = NULL;
oa::oaLib                           *Synthesis::currentLibrary = NULL;
oa::oaView                          *Synthesis::currentView = NULL;
Manager                             *Synthesis::currentManager = NULL;
oa::oaModule                        *Synthesis::currentModule = NULL;
bool                                 Synthesis::overwriteStructure = true;

list<oa::oaLib*>                     Synthesis::leafLibs;
list<oa::oaScalarName>               Synthesis::leafViews;


// ***************************************************************************** 
// setOverwriteStructure() 
// 
// ***************************************************************************** 
void
Synthesis::setOverwriteStructure(bool overwrite) {
    overwriteStructure = overwrite;
}


// *****************************************************************************
// zeroExpand()
//
//
// *****************************************************************************
void 
Synthesis::zeroExpand(MultiRefBus &l1, MultiRefBus &l2) {
    if(l1.size() < l2.size()) {
        for(int i=l2.size()-l1.size(); i>0; i--) {
            l1.push_front( constantZero() );
        }
    } else if(l1.size() > l2.size()) {
        for(int i=l1.size()-l2.size(); i>0; i--) {
            l2.push_front( constantZero() );
        }
    }
}



bool
Synthesis::checkForExistenceOfDesign(oa::oaScalarName libName,
                                     oa::oaScalarName cellName,
                                     oa::oaScalarName viewName)
{
    try {
        oa::oaDesign *design;
        design = oa::oaDesign::open(libName, cellName, viewName, 'a');
        design->close();
        return true;
    } catch (oa::oaException &e) {
        return false;
    }
}


// *****************************************************************************
// findModule()
//
//
// *****************************************************************************
oa::oaModule*           
Synthesis::findModule(const string identifier) {
    assert(nameSpace);

    DEBUG_PRINTLN("find module " << identifier);

    if (!currentLibrary || !currentView) {
      cerr << "ERROR: The design library and view both must first be set" << endl;
      QUIT_ON_ERROR;
    }

    oa::oaScalarName    cellName(*nameSpace, identifier.c_str());

    // 1. a module in the current design (if it exists)
    if (currentModule) {
        oa::oaModule *module = oa::oaModule::find(currentModule->getDesign(), cellName);
        if (module) {
            return module;
        }
    }

    // 2. search current design library
    oa::oaNativeNS      nativeNS;
    oa::oaScalarName    libName;
    currentLibrary->getName(libName);
    oa::oaScalarName    viewName;
    currentView->getName(viewName);

    oa::oaDesign *design;
    
    // find or open design
    if ((design = oa::oaDesign::find(libName, cellName, viewName))) {
        return design->getTopModule();
    } else {
        try {
            design = oa::oaDesign::open(libName, cellName, viewName, 'a');
            assert(design);
            oa::oaModule *module = design->getTopModule();
            return module;
        } catch (oa::oaException &e) {
        }
    }

    // 3. search leaf libraries
    for(list<oa::oaLib*>::iterator libIter=leafLibs.begin();
        libIter!=leafLibs.end(); libIter++) {
      oa::oaLib *leafLib = *libIter;
      oa::oaScalarName leafLibName;
      leafLib->getName(leafLibName);

      // search each view
      for(list<oa::oaScalarName>::iterator viewIter=leafViews.begin();
          viewIter!=leafViews.end(); viewIter++) {

        if ((design = oa::oaDesign::find(leafLibName, cellName, *viewIter))) {
            return design->getTopModule();
        }

        try {
            design = oa::oaDesign::open(leafLibName, cellName, *viewIter, 'r');
            assert(design);
            oa::oaModule *module = design->getTopModule();
            return module;
        } catch (oa::oaException &e) {
            // design didn't exist
        }
      }

      cout << endl;
    }
    
    return NULL;
}


// *****************************************************************************
// createModule()
//
//
// *****************************************************************************
oa::oaModule*           
Synthesis::createModule(const string identifier) {
    assert(nameSpace);

    DEBUG_PRINTLN("create module " << identifier);

    if (!currentLibrary || !currentView) {
      cerr << "ERROR: The design library and view both must first be set" << endl;
      QUIT_ON_ERROR;
    }

    oa::oaScalarName    cellName(*nameSpace, identifier.c_str());

    // open design
    oa::oaNativeNS      nativeNS;
    oa::oaScalarName    libName;
    currentLibrary->getName(libName);
    oa::oaScalarName    viewName;
    currentView->getName(viewName);
    oa::oaViewType     *viewType = oa::oaViewType::get(oa::oacNetlist);
    oa::oaDesign       *design;
    
    // find or create design
    if ((design = oa::oaDesign::find(libName, cellName, viewName))) {
        return design->getTopModule();
    } else {
        try {
            design = oa::oaDesign::open(libName, cellName, viewName, 'a');
        } catch (oa::oaException &e) {
            // create
            design = oa::oaDesign::open(libName, cellName, viewName, viewType, 'w');
        }
    }
    if (!design) {
      cerr << "ERROR: Could not find/open design: " << identifier << endl;
      QUIT_ON_ERROR;
    }
        
    // get/create top module
    oa::oaModule *module = design->getTopModule();
    if (!module) {
        module = oa::oaModule::create(design, cellName);
        design->setTopModule(module);
    } else {

        // any existing structure needs to be discarded (if overwriteStructure)
        if (overwriteStructure) {
            // destroy the existing design and create a new one
            design->purge();
            if (checkForExistenceOfDesign(libName, cellName, viewName)) {
                oa::oaDesign::destroy(libName, cellName, viewName);
            }
            design = oa::oaDesign::open(libName, cellName, viewName, viewType, 'w');
            module = oa::oaModule::create(design, cellName); 
            design->setTopModule(module); 
        }

        // any existing functional information needs to be discarded

        // clear existing manager
        if (oagFpga::Manager::hasManager(design)) {
            oagFpga::Manager *manager = oagFpga::Manager::get(design);
            assert(manager);
            delete manager;
            managerAppDef->destroy(design);
        }

        // clear connections from nets to nodes
        oa::oaModNet *net;
        oa::oaIter<oa::oaModNet> netIter(module->getNets(oacNetIterSingleBit));
        while ((net = netIter.getNext())) {
            bbRefAppDef->destroy(net);
        }
    }
    assert(module);

    // create global "tie0" and "tie1" nets if they don't exist
    oa::oaScalarName tie0Name(nativeNS, "tie0");
    if (oa::oaModScalarNet::find(module, tie0Name) == NULL) {
        oa::oaModScalarNet::create(module, tie0Name, oa::oacTieLoSigType, false);
    }
    oa::oaScalarName tie1Name(nativeNS, "tie1");
    if (oa::oaModScalarNet::find(module, tie1Name) == NULL) {
        oa::oaModScalarNet::create(module, tie1Name, oa::oacTieHiSigType, false);
    }

    return module;
}


// *****************************************************************************
// instantiateModule()
//
// *****************************************************************************
oa::oaModInst*          
Synthesis::instantiateModule(oa::oaDesign *master, const string name) {
    assert(nameSpace);
    assert(currentModule);
    assert(master);

    // find or create design
    oa::oaModInst *inst;
    if (name.empty()) {
        inst = oa::oaModScalarInst::create(currentModule, master);
    } else {
        inst = oa::oaModScalarInst::create(currentModule, master, 
                                           oa::oaScalarName(*nameSpace,name.c_str()));
    }

    return inst;
}
    

// *****************************************************************************
// createScalarNet()
//
//
// *****************************************************************************
oa::oaModScalarNet*
Synthesis::createScalarNet(const string identifier) {
    assert(nameSpace);
    assert(currentModule);

    // does this net exist?
    oa::oaScalarName netName(*nameSpace, oa::oaString(identifier.c_str()));
    oa::oaModScalarNet *net = oa::oaModScalarNet::find(currentModule, netName);
    if (!net) {
        // create the net
        net = oa::oaModScalarNet::create(currentModule, netName);
    }

    // create a terminal node if module has functional description
    if (currentManager != NULL) {
        currentManager->setNetToBBConnection(net, 
            currentManager->bbg.newTerminal( currentManager->bbg.getNull()) );
    }

    return net;
}


// *****************************************************************************
// createBusNet()
//
//
// *****************************************************************************
oa::oaModBusNet*
Synthesis::createBusNet(const string identifier, int start, int stop) {
    assert(nameSpace);
    assert(currentModule);
    
    oa::oaScalarName netName(*nameSpace, oa::oaString(identifier.c_str()));
    
    // does a bus net of this name already exist?
    oa::oaModBusNet *bus = oa::oaModBusNet::find(currentModule, netName, start, stop, 1);
    if (bus) {
        cerr << "ERROR: net " << identifier << " defined twice" << endl;
        QUIT_ON_ERROR;
    }
    
    // create the net
    bus = oa::oaModBusNet::create(currentModule, netName, start, stop, 1);

#ifdef DEBUG
    oa::oaString modName;
    currentModule->getName(oa::oaVerilogNS(), modName);

    oa::oaString str;
    bus->getName(oa::oaVerilogNS(), str);
    DEBUG_PRINTLN("BusNet created: " << str);
    DEBUG_PRINTLN("currentManager = " << currentManager);
#endif

    // create terminal BB nodes if functional manager exists
    if (currentManager != NULL) {
#ifdef DEBUG
        DEBUG_PRINTLN("createBusNet, create terminal BB nodes");
#endif
        for(int b = 0; b<=abs(stop-start); b++) {
            currentManager->setNetToBBConnection(bus->getBit(b), 
                currentManager->bbg.newTerminal(currentManager->bbg.getNull()) );
        }
    }

    return bus;
}


// *****************************************************************************
// createTerm()
//
//
// *****************************************************************************
oa::oaModTerm*
Synthesis::createTerm(oa::oaModNet *net, const string identifier, 
        oa::oaTermType type, unsigned int portPosition) {
    assert(nameSpace);
    assert(net);
    
    if (type == oa::oacInputOutputTermType) {
       cerr << "WARNING: Functionality not supported for inout ports" << endl;
    }
    
    oa::oaModTerm *term;

    oa::oaModule *module = net->getModule();
    oa::oaUInt4 numBits = net->getNumBits();
    oa::oaModTerm *newTerm = 0;
    
    // create term
    if (numBits == 1) {
        oa::oaScalarName sName(*nameSpace, identifier.c_str());
        term = oa::oaModTerm::find(module, sName);
        if (!term) {
            newTerm = oa::oaModTerm::create(net, sName, type);
        }
    } else {
        oa::oaVectorName vName(*nameSpace, identifier.c_str(), 0, numBits - 1);
        term = oa::oaModTerm::find(module, vName);
        if (!term) {
            newTerm = oa::oaModTerm::create(net, vName, type);
        }
    }

    if (term) {
        // FIXME perhaps we should do more checking here to make sure the
        // term has the right direction, bus width, position, etc.
        return term;
    }

    // set port position if given
    if (portPosition != oacNullIndex) {
        newTerm->setPosition(portPosition);
    }
    return newTerm;
}   


// *****************************************************************************
// findBusNet()
//
//
// *****************************************************************************
oa::oaModBusNet*
Synthesis::findBusNet(const string identifier) {
    assert(currentModule);
    assert(nameSpace);

    oa::oaScalarName baseName(*nameSpace,identifier.c_str());

    oa::oaModBusNetDef *busNetDef = oa::oaModBusNetDef::find(currentModule, baseName);
    if (busNetDef) {
        oa::oaIter<oa::oaModBusNet> busIter(busNetDef->getBusNets());
        oa::oaModBusNet *busNet = busIter.getNext();
        if (busNet) {
            return busNet;
        }
    }

    return NULL;
}


// *****************************************************************************
// findBusNetBit()
//
//
// *****************************************************************************
oa::oaModBusNetBit*
Synthesis::findBusNetBit(const string identifier, const int bit) {
    assert(nameSpace);
    assert(currentModule);

    // create the net
    oa::oaScalarName netName(*nameSpace, identifier.c_str());
    return oa::oaModBusNetBit::find(currentModule, netName, bit);
}


// *****************************************************************************
// findScalarNet()
//
//
// *****************************************************************************
oa::oaModScalarNet*
Synthesis::findScalarNet(const string identifier) {
    assert(nameSpace);
    assert(currentModule);

    // create the net
    oa::oaScalarName netName(*nameSpace, identifier.c_str());
    return oa::oaModScalarNet::find(currentModule, netName);
}


// *****************************************************************************
// findNet()
//
//
// *****************************************************************************
oa::oaModNet*
Synthesis::findNet(const string identifier) {
  oa::oaModNet *net;
  net = findScalarNet(identifier);
  if (!net)
    net = findBusNet(identifier);  
  return net;
}


// *****************************************************************************
// assignMultiRef()
//
//
// *****************************************************************************
void
Synthesis::assignMultiRef(oa::oaModBitNet *net, const MultiRef e) {
    assert(nameSpace);
    assert(net);
    
    oa::oaString str;
    net->getName(*nameSpace, str);
    
    // has this net already been assigned?
    // (a terminal node's driver should be NULL_BBREF it's unassigned)
    if (currentManager && net->getAppDefs().includes(bbRefAppDef)) {
        BBRef node = bbRefAppDef->get(net);
        if (!currentManager->bbg.isNull(currentManager->bbg.getTerminalDriver(node))) {
            cerr << "ERROR: net " << str << " is being assigned more than once" << endl;
            QUIT_ON_ERROR;
        }
    }
    
    if (e.type == BBREF) {
        assert(currentManager);
        // if we're being asked to assign an BBREF, 
        // we know this module must already be functional
        assert( net->getAppDefs().includes(bbRefAppDef) );
    
        BBRef node = bbRefAppDef->get(net);
        
        // repoint the node to the MultiRef
        currentManager->bbg.setTerminalDriver(node, e.bb);
        DEBUG_PRINTLN("\t\t . " << node << "," << str << " (functional) = " << e.bb)
    } else {

        net->makeEquivalent(e.net);

        DEBUG_PRINTLN("\t\t . " << str << " (structural)")
    }
}


// *****************************************************************************
// notOf()
//
//
// *****************************************************************************
MultiRef
Synthesis::notOf(MultiRef e) {
    assert(currentModule);

    // have we created a functional manager for this design yet?
    if (currentManager == NULL) {
        currentManager = Manager::get(currentModule->getDesign());
    }

    // if this MultiRef is a net, convert it to a BBRef
    if (e.type == NET) {
        // there must already be an existing BBRef
        oa::oaModBitNet *net = e.net;
        assert(net);
        assert(net->getAppDefs().includes(bbRefAppDef));
        e.bb = bbRefAppDef->get(net);
        e.type = BBREF;
    }

    assert(e.type == BBREF);
    return MultiRef(currentManager->bbg.unaryOpt(RtlNode::BITWISE_NOT, e.bb));
}

// *****************************************************************************
// binaryOpt()
//
//
// *****************************************************************************
MultiRef
Synthesis::binaryOpt(RtlNode::OptType optType, MultiRef e1, MultiRef e2) {
    assert(currentModule);

    // have we created a functional manager for this design yet?
    if (currentManager == NULL) {
        currentManager = Manager::get(currentModule->getDesign());
    }

    // if this either MultiRef is a net, convert it to a BBRef
    if (e1.type == NET) {
        // there must already be an existing BBRef
        oa::oaModBitNet *net = e1.net;
        assert(net);
        assert(net->getAppDefs().includes(bbRefAppDef));
        e1.bb = bbRefAppDef->get(net);
        e1.type = BBREF;
    }
    if (e2.type == NET) {
        // there must already be an existing BBRef
        oa::oaModBitNet *net = e2.net;
        assert(net);
        assert(net->getAppDefs().includes(bbRefAppDef));
        e2.bb = bbRefAppDef->get(net);
        e2.type = BBREF;
    }
    
    assert(e1.type == BBREF);
    assert(e2.type == BBREF);

    return MultiRef(currentManager->bbg.binaryOpt(optType, e1.bb, e2.bb));
}

// *****************************************************************************
// andOf()
//
//
// *****************************************************************************
MultiRef
Synthesis::andOf(MultiRef e1, MultiRef e2) {
    return binaryOpt(RtlNode::BITWISE_AND, e1, e2);
}


// *****************************************************************************
// orOf()
//
//
// *****************************************************************************
MultiRef
Synthesis::orOf(MultiRef e1, MultiRef e2) {
    return binaryOpt(RtlNode::BITWISE_OR, e1, e2);
}


// *****************************************************************************
// xorOf()
//
//
// *****************************************************************************
MultiRef
Synthesis::xorOf(MultiRef e1, MultiRef e2) {
    return binaryOpt(RtlNode::BITWISE_XOR, e1, e2);
}

// *****************************************************************************
// norOf()
//
//
// *****************************************************************************
MultiRef
Synthesis::norOf(MultiRef e1, MultiRef e2) {
    return binaryOpt(RtlNode::BITWISE_NOR, e1, e2);
}

// *****************************************************************************
// nandOf()
//
//
// *****************************************************************************
MultiRef
Synthesis::nandOf(MultiRef e1, MultiRef e2) {
    return binaryOpt(RtlNode::BITWISE_NAND, e1, e2);
}

// *****************************************************************************
// xnorOf()
//
//
// *****************************************************************************
MultiRef
Synthesis::xnorOf(MultiRef e1, MultiRef e2) {
    return binaryOpt(RtlNode::BITWISE_XNOR, e1, e2);
}

// *****************************************************************************
// connectPort()
//
//
// *****************************************************************************
void
Synthesis::connectPort(oa::oaModInst *inst, oa::oaModNet *net, 
                       unsigned int portPosition) {
    oa::oaModInstTerm::create(net, inst, portPosition);

    // check that port widths match
    oa::oaModule *module = inst->getMasterModule();
    assert(module);
    oa::oaModTerm *term = oa::oaModTerm::find(module, portPosition);
    assert(term);
    if(term->getNumBits() != net->getNumBits()) {
        cout << "ERROR: Port connection width mismatch" << endl;
        QUIT_ON_ERROR;
    }
}


// *****************************************************************************
// connectPort()
//
//
// *****************************************************************************
void 
Synthesis::connectPort(oa::oaModInst *inst, oa::oaModNet *net, 
                       const string portString) {
    assert(nameSpace);
    
    oa::oaName netName, termName;
    net->getName(netName);
    if (net->getNumBits() == 1) {
        termName = oa::oaScalarName(*nameSpace, portString.c_str());
        oa::oaModInstTerm::create(net, inst, termName);
  
    } else if (netName.getType() == oa::oacVectorNameType) {
        termName = oa::oaVectorName(*nameSpace, portString.c_str(), 0,net->getNumBits()-1);
        oa::oaModInstTerm::create(net, inst, termName);
    } else {
        QUIT_ON_INTERNAL_ERROR;
    }
    
    // check that port widths match
    oa::oaModule *module = inst->getMasterModule();
    assert(module);
    oa::oaModTerm *term = oa::oaModTerm::find(module, termName);
    assert(term);
    if(term->getNumBits() != net->getNumBits()) {
        cout << "ERROR: Port connection width mismatch" << endl;
        QUIT_ON_ERROR;
    }
}

// *****************************************************************************
// unaryBusOpt()
//
// *****************************************************************************

MultiRef
Synthesis::unaryBusOpt(RtlNode::OptType optType, MultiRefBus &l) {
    assert(currentModule);
    assert(l.size() > 0);
    
    // have we created a functional manager for this design yet?
    if (currentManager == NULL) {
        currentManager = Manager::get(currentModule->getDesign());
    }
    
    MultiRefBus::iterator multiRefIter;
    vector<BBRef> driverBBRefs;
    for(multiRefIter = l.begin(); multiRefIter != l.end(); ++ multiRefIter){

        MultiRef multiRef = *multiRefIter;

        if(multiRef.type == NET){
            // there must already be an existing BBRef
            oa::oaModBitNet *net = multiRef.net;
            assert(net);
            assert(net->getAppDefs().includes(bbRefAppDef));
            multiRef.bb = bbRefAppDef->get(net);
            multiRef.type = BBREF;
        }

        assert(multiRef.type == BBREF);
 
        // setup one input of this reduction operator
        driverBBRefs.push_back(multiRef.bb);
    }
    return MultiRef(currentManager->bbg.unaryBusOpt(optType, driverBBRefs));
}


// *****************************************************************************
// reductionOr()
//
// *****************************************************************************
MultiRef
Synthesis::reductionOr(MultiRefBus &l) {
    if(l.size() == 1) return *l.begin();
    return unaryBusOpt(RtlNode::REDUCTION_OR, l);
}


// *****************************************************************************
// reductionXor()
//
// *****************************************************************************
MultiRef
Synthesis::reductionXor(MultiRefBus &l) {
    assert(l.size() > 1);
    return unaryBusOpt(RtlNode::REDUCTION_XOR, l);
}

// *****************************************************************************
// reductionAnd()
//
// *****************************************************************************
MultiRef
Synthesis::reductionAnd(MultiRefBus &l) {
    if(l.size() == 1) return *l.begin();
    return unaryBusOpt(RtlNode::REDUCTION_AND, l);
}

// *****************************************************************************
// reductionNand()
//
// *****************************************************************************
MultiRef
Synthesis::reductionNand(MultiRefBus &l) {
    return unaryBusOpt(RtlNode::REDUCTION_NAND, l);
}

// *****************************************************************************
// reductionNor()
//
// *****************************************************************************
MultiRef
Synthesis::reductionNor(MultiRefBus &l) {
    return unaryBusOpt(RtlNode::REDUCTION_NOR, l);
}

// *****************************************************************************
// reductionXnor()
//
// *****************************************************************************
MultiRef
Synthesis::reductionXnor(MultiRefBus &l) {
    return unaryBusOpt(RtlNode::REDUCTION_XNOR, l);
}

// *****************************************************************************
// logicNOT()
//
//
// *****************************************************************************
MultiRef
Synthesis::logicNot(MultiRefBus &l) {
    return unaryBusOpt(RtlNode::LOGICAL_NOT,l); 
}
// *****************************************************************************
// constantZero()
//
//
// *****************************************************************************
MultiRef
Synthesis::constantZero() {
    oa::oaNativeNS      nativeNS;
    oa::oaScalarName    name(nativeNS, "tie0");
    MultiRef e(oa::oaModScalarNet::find(currentModule, name));
    return e;
}


// *****************************************************************************
// constantOne()
//
//
//
// *****************************************************************************
MultiRef
Synthesis::constantOne() {
    oa::oaNativeNS      nativeNS;
    oa::oaScalarName    name(nativeNS, "tie1");
    MultiRef e(oa::oaModScalarNet::find(currentModule, name));
    return e;
}

// *****************************************************************************
// binaryBusOpt()
//
//
// *****************************************************************************
MultiRef
Synthesis::binaryBusOpt(RtlNode::OptType optType, MultiRefBus &l1, MultiRefBus &l2) {
    assert(l1.size() == l2.size() && l1.size() > 0);

     // have we created a functional manager for this design yet?
    if (currentManager == NULL) {
        currentManager = Manager::get(currentModule->getDesign());
    }
    
    MultiRefBus::iterator multiRefIter;
    vector<BBRef> driverBBRefs1;
    for(multiRefIter = l1.begin(); multiRefIter != l1.end(); ++ multiRefIter){

        MultiRef multiRef = *multiRefIter;

        if(multiRef.type == NET){
            // there must already be an existing BBRef
            oa::oaModBitNet *net = multiRef.net;
            assert(net);
            assert(net->getAppDefs().includes(bbRefAppDef));
            multiRef.bb = bbRefAppDef->get(net);
            multiRef.type = BBREF;
        }

        assert(multiRef.type == BBREF);
 
        // setup one input of this reduction operator
        driverBBRefs1.push_back(multiRef.bb);
    }
    vector<BBRef> driverBBRefs2;
    for(multiRefIter = l2.begin(); multiRefIter != l2.end(); ++ multiRefIter){

        MultiRef multiRef = *multiRefIter;

        if(multiRef.type == NET){
            // there must already be an existing BBRef
            oa::oaModBitNet *net = multiRef.net;
            assert(net);
            assert(net->getAppDefs().includes(bbRefAppDef));
            multiRef.bb = bbRefAppDef->get(net);
            multiRef.type = BBREF;
        }

        assert(multiRef.type == BBREF);
 
        // setup one input of this reduction operator
        driverBBRefs2.push_back(multiRef.bb);
    }
    return MultiRef(currentManager->bbg.binaryBusOpt(optType,
                driverBBRefs1, driverBBRefs2));

}


// *****************************************************************************
// lessThan()
//
//
// *****************************************************************************
MultiRef
Synthesis::lessThan(MultiRefBus &l1, MultiRefBus &l2) {
    return binaryBusOpt(RtlNode::LESS_THAN, l1, l2);

}


// *****************************************************************************
// equalTo()
//
//
// *****************************************************************************
MultiRef
Synthesis::equalTo(MultiRefBus &l1, MultiRefBus &l2) {
    return binaryBusOpt(RtlNode::EQUAL,l1, l2); 
}

// *****************************************************************************
// lessThan()
//
//
// *****************************************************************************
MultiRef
Synthesis::lessThanEqual(MultiRefBus &l1, MultiRefBus &l2) {
    return binaryBusOpt(RtlNode::LESS_THAN_EQUAL, l1, l2);

}

// *****************************************************************************
// greaterThan()
//
//
// *****************************************************************************
MultiRef
Synthesis::greaterThan(MultiRefBus &l1, MultiRefBus &l2) {
    return binaryBusOpt(RtlNode::GREATER_THAN, l1, l2);

}

// *****************************************************************************
// greaterThanEqual()
//
//
// *****************************************************************************
MultiRef
Synthesis::greaterThanEqual(MultiRefBus &l1, MultiRefBus &l2) {
    return binaryBusOpt(RtlNode::GREATER_THAN_EQUAL, l1, l2);

}

// *****************************************************************************
// notEuqalTo()
//
//
// *****************************************************************************
MultiRef
Synthesis::notEqualTo(MultiRefBus &l1, MultiRefBus &l2) {
    return binaryBusOpt(RtlNode::NOTEQUAL, l1, l2);

}

// *****************************************************************************
// logicAnd()
//
//
// *****************************************************************************
MultiRef
Synthesis::logicAnd(MultiRefBus &l1, MultiRefBus &l2) {
    return binaryBusOpt(RtlNode::LOGICAL_AND,l1, l2); 
}

// *****************************************************************************
// logicOr()
//
//
// *****************************************************************************
MultiRef
Synthesis::logicOr(MultiRefBus &l1, MultiRefBus &l2) {
    return binaryBusOpt(RtlNode::LOGICAL_OR,l1, l2); 
}

// *****************************************************************************
// unaryBusInputOutputOpt()
//
// *****************************************************************************
void
Synthesis::unaryBusInputOutputOpt(RtlNode::OptType optType, int numOutBits,
        MultiRefBus &result, MultiRefBus &l) {

    result.clear();

    // have we created a functional manager for this design yet?
    if (currentManager == NULL) {
        currentManager = Manager::get(currentModule->getDesign());
    }
    
    MultiRefBus::iterator multiRefIter;
    vector<BBRef> driverBBRefs;
    for(multiRefIter = l.begin(); multiRefIter != l.end(); ++ multiRefIter){

        MultiRef multiRef = *multiRefIter;

        if(multiRef.type == NET){
            // there must already be an existing BBRef
            oa::oaModBitNet *net = multiRef.net;
            assert(net);
            assert(net->getAppDefs().includes(bbRefAppDef));
            multiRef.bb = bbRefAppDef->get(net);
            multiRef.type = BBREF;
        }

        assert(multiRef.type == BBREF);
 
        // setup one input of this operator
        driverBBRefs.push_back(multiRef.bb);
    }

    // create a BB node
    vector<BBRef> outputBBRefs;
    currentManager->bbg.unaryBusInputOutputOpt(optType, numOutBits,
            driverBBRefs, outputBBRefs);

    // setup outputs (result)
    vector<BBRef>::iterator bbRefIter;
    for(bbRefIter = outputBBRefs.begin(); bbRefIter != outputBBRefs.end();
            ++ bbRefIter) {
        result.push_front(MultiRef(*bbRefIter));
    }

}

// *****************************************************************************
// binaryBusInputOutputOpt()
//
// *****************************************************************************
void
Synthesis::binaryBusInputOutputOpt(RtlNode::OptType optType, int numOutBits,
        MultiRefBus &result, MultiRefBus &l1, MultiRefBus &l2) {

    result.clear();

    // have we created a functional manager for this design yet?
    if (currentManager == NULL) {
        currentManager = Manager::get(currentModule->getDesign());
    }
    
    MultiRefBus::iterator multiRefIter;
    vector<BBRef> driverBBRefs1;
    for(multiRefIter = l1.begin(); multiRefIter != l1.end(); ++ multiRefIter){

        MultiRef multiRef = *multiRefIter;

        if(multiRef.type == NET){
            // there must already be an existing BBRef
            oa::oaModBitNet *net = multiRef.net;
            assert(net);

#ifdef DEBUG
            oa::oaString str;
            net->getName(oa::oaVerilogNS(), str);
            DEBUG_PRINTLN("binaryBusInputOutputOpt: " << str);
#endif
            assert(net->getAppDefs().includes(bbRefAppDef));
            multiRef.bb = bbRefAppDef->get(net);
            multiRef.type = BBREF;
        }

        assert(multiRef.type == BBREF);
 
        // setup one input of this operator
        driverBBRefs1.push_back(multiRef.bb);
    }
    vector<BBRef> driverBBRefs2;
    for(multiRefIter = l2.begin(); multiRefIter != l2.end(); ++ multiRefIter){

        MultiRef multiRef = *multiRefIter;

        if(multiRef.type == NET){
            // there must already be an existing BBRef
            oa::oaModBitNet *net = multiRef.net;
            assert(net);
            assert(net->getAppDefs().includes(bbRefAppDef));
            multiRef.bb = bbRefAppDef->get(net);
            multiRef.type = BBREF;
        }

        assert(multiRef.type == BBREF);
 
        // setup one input of this operator
        driverBBRefs2.push_back(multiRef.bb);
    }

    // create a BB node
    vector<BBRef> outputBBRefs;
    currentManager->bbg.binaryBusInputOutputOpt(optType, numOutBits,
            driverBBRefs1, driverBBRefs2, outputBBRefs);

    // setup outputs (result)
    vector<BBRef>::iterator bbRefIter;
    for(bbRefIter = outputBBRefs.begin(); bbRefIter != outputBBRefs.end();
            ++ bbRefIter) {
        result.push_front(MultiRef(*bbRefIter));
    }

}

// *****************************************************************************
// arithmeticAdd()
//
// *****************************************************************************
void
Synthesis::arithmeticAdd(MultiRefBus &result, MultiRefBus &l1, MultiRefBus &l2) {
    assert(l1.size() == l2.size());
    //binaryBusInputOutputOpt(RtlNode::ADD, l1.size(), result, l1, l2);
    binaryBusInputOutputOpt(RtlNode::ADD, l1.size()+1, result, l1, l2);
}


// *****************************************************************************
// arithmeticSubtract()
//
//
// *****************************************************************************
void
Synthesis::arithmeticSubtract(MultiRefBus &result, MultiRefBus &l1, MultiRefBus &l2) {
    assert(l1.size() == l2.size());
    binaryBusInputOutputOpt(RtlNode::SUBTRACT, l1.size(), result, l1, l2);
}


// *****************************************************************************
// arithmeticMultiply()
//
//
// *****************************************************************************
void
Synthesis::arithmeticMultiply(MultiRefBus &result, MultiRefBus &l1, MultiRefBus &l2) {
    binaryBusInputOutputOpt(RtlNode::MULTIPLY, l1.size()+l2.size(), result, l1, l2);
}


// *****************************************************************************
// arithmeticDivide()
//
//
// *****************************************************************************
void        
Synthesis::arithmeticDivide(MultiRefBus &result, MultiRefBus &l1, MultiRefBus &l2) {
    binaryBusInputOutputOpt(RtlNode::DIVIDE, l1.size(), result, l1, l2);
}


// *****************************************************************************
// arithmeticDivide()
//
//
// *****************************************************************************
void
Synthesis::arithmeticModulo(MultiRefBus &result, MultiRefBus &l1, MultiRefBus &l2) {
    binaryBusInputOutputOpt(RtlNode::MODULO, l2.size(), result, l1, l2);
}

// *****************************************************************************
// leftShift()
//
// *****************************************************************************
void
Synthesis::leftShift(MultiRefBus &result, MultiRefBus &l1, MultiRefBus &l2) {
    binaryBusInputOutputOpt(RtlNode::LEFT_SHIFT, l2.size(), result, l1, l2);
}

// *****************************************************************************
// latch()
//
//
// *****************************************************************************
MultiRef
Synthesis::latch(MultiRef enable, MultiRef in, const string name) {
    assert(nameSpace);
    assert(currentModule);
    static_cast<void>(name);

    // have we created a functional manager for this design yet?
    if (currentManager == NULL) {
        currentManager = Manager::get(currentModule->getDesign());
    }

    // if this MultiRef is a net, convert it to a BBRef
    if (in.type == NET) {
        // there must already be an existing BBRef
        oa::oaModBitNet *net = in.net;
        assert(net);
        assert(net->getAppDefs().includes(bbRefAppDef));
        in.bb = bbRefAppDef->get(net);
        in.type = BBREF;
    }

    return MultiRef(currentManager->bbg.bitSeq(RtlNode::LATCH, in.bb, enable.bb,
                currentManager->bbg.getNull(),
                currentManager->bbg.getNull()));
}

// *****************************************************************************
// seq()
//
//
// *****************************************************************************
MultiRef
Synthesis::seq(MultiRef in, MultiRef clock, const string name) {
    assert(nameSpace);
    assert(currentModule);
    static_cast<void>(name);

    // have we created a functional manager for this design yet?
    if (currentManager == NULL) {
        currentManager = Manager::get(currentModule->getDesign());
    }

    // if in is a net, convert it to a BBRef
    if (in.type == NET) {
        // there must already be an existing BBRef
        oa::oaModBitNet *net = in.net;
        assert(net);
        assert(net->getAppDefs().includes(bbRefAppDef));
        in.bb = bbRefAppDef->get(net);
        in.type = BBREF;
    }
    if (clock.type == NET) {
        // there must already be an existing BBRef
        oa::oaModBitNet *net = clock.net;
        assert(net);
        assert(net->getAppDefs().includes(bbRefAppDef));
        clock.bb = bbRefAppDef->get(net);
        clock.type = BBREF;
    }

    DEBUG_PRINTLN("\t\t\t created state bit")

    return MultiRef(currentManager->bbg.bitSeq(RtlNode::DFF, in.bb, clock.bb,
                currentManager->bbg.getNull(), 
                currentManager->bbg.getNull()));
}


// *****************************************************************************
// seq()
//
//
// *****************************************************************************
MultiRef
Synthesis::seq(MultiRef in, MultiRef clock, MultiRef aLoad, MultiRef aData, 
        const string name) {
    assert(nameSpace);
    assert(currentModule);
    static_cast<void>(name);

    // have we created a functional manager for this design yet?
    if (currentManager == NULL) {
        currentManager = Manager::get(currentModule->getDesign());
    }

    // if in is a net, convert it to a BBRef
    if (in.type == NET) {
        // there must already be an existing BBRef
        oa::oaModBitNet *net = in.net;
        assert(net);
        assert(net->getAppDefs().includes(bbRefAppDef));
        in.bb = bbRefAppDef->get(net);
        in.type = BBREF;
    }
    // if clock is a net, convert it to a BBRef
    if (clock.type == NET) {
        // there must already be an existing BBRef
        oa::oaModBitNet *net = clock.net;
        assert(net);
        assert(net->getAppDefs().includes(bbRefAppDef));
        clock.bb = bbRefAppDef->get(net);
        clock.type = BBREF;
    }
    // if aLoad is a net, convert it to a BBRef
    if (aLoad.type == NET) {
        // there must already be an existing BBRef
        oa::oaModBitNet *net = aLoad.net;
        assert(net);
        assert(net->getAppDefs().includes(bbRefAppDef));
        aLoad.bb = bbRefAppDef->get(net);
        aLoad.type = BBREF;
    }
    // if aData is a net, convert it to a BBRef
    if (aData.type == NET) {
        // there must already be an existing BBRef
        oa::oaModBitNet *net = aData.net;
        assert(net);
        assert(net->getAppDefs().includes(bbRefAppDef));
        aData.bb = bbRefAppDef->get(net);
        aData.type = BBREF;
    }

    DEBUG_PRINTLN("\t\t\t created state bit")

    return MultiRef(currentManager->bbg.bitSeq(RtlNode::DFF, in.bb, clock.bb,
                aLoad.bb, aData.bb));
}


/*
// *****************************************************************************
// annotateAsynchronousSignal()
//
//
// *****************************************************************************
void
Synthesis::annotateAsynchronousSignal(oagAi::Ref sequential, const string label, MultiRef signal) {
    assert(currentManager);

    // TODO: check back to see whether we need this

    // if the MultiRef is a net, convert it to an oagAi::Ref
    if (signal.type == NET) {
        // there must already be an existing oagAi::Ref
        oa::oaModBitNet *net = signal.net;
        assert(net);
        assert(net->getAppDefs().includes(AiRefAppDef));
        signal.ai = AiRefAppDef->get(net);
        signal.type = AIREF;
    }
    
    // annotate the asynchronous input
    DEBUG_PRINTLN("\tannotating node " << sequential 
                  << " with asychronous signal " << label 
                  << " = " << signal.ai);
    oagAi::Node::SequentialData *seqData = currentManager->ai.getSequentialData(sequential);
    assert(seqData);
    assert(seqData->abstractionLevel == oagAi::Node::SequentialData::BLACK_BOX);
    seqData->signals[label] = signal.ai;
}
*/
    
// *****************************************************************************
// mux()
//
//
// *****************************************************************************
MultiRef
Synthesis::mux(MultiRef sel, MultiRef in0, MultiRef in1) {

    if (in0 == in1) {
        return in0;
    }

    // have we created a functional manager for this design yet?
    if (currentManager == NULL) {
        currentManager = Manager::get(currentModule->getDesign());
    }

    // if in0 is a net, convert it to a BBRef
    if (in0.type == NET) {
        // there must already be an existing BBRef
        oa::oaModBitNet *net = in0.net;
        assert(net);
        assert(net->getAppDefs().includes(bbRefAppDef));
        in0.bb = bbRefAppDef->get(net);
        in0.type = BBREF;
    }
    // if in1 is a net, convert it to a BBRef
    if (in1.type == NET) {
        // there must already be an existing BBRef
        oa::oaModBitNet *net = in1.net;
        assert(net);
        assert(net->getAppDefs().includes(bbRefAppDef));
        in1.bb = bbRefAppDef->get(net);
        in1.type = BBREF;
    }
    // if sel is a net, convert it to a BBRef
    if (sel.type == NET) {
        // there must already be an existing BBRef
        oa::oaModBitNet *net = sel.net;
        assert(net);
        assert(net->getAppDefs().includes(bbRefAppDef));
        sel.bb = bbRefAppDef->get(net);
        sel.type = BBREF;
    }

    return MultiRef(currentManager->bbg.bitMux(in0.bb, in1.bb, sel.bb));
}

// *****************************************************************************
// mux()
//
//
// *****************************************************************************
MultiRef
Synthesis::mux(MultiRefBus& select, MultiRefBus &in0) {

    // have we created a functional manager for this design yet?
    if (currentManager == NULL) {
        currentManager = Manager::get(currentModule->getDesign());
    }
    
    MultiRefBus::iterator multiRefIter;
    vector<BBRef> driverBBRefs1;
    for(multiRefIter = in0.begin(); multiRefIter != in0.end(); ++ multiRefIter){

        MultiRef multiRef = *multiRefIter;

        if(multiRef.type == NET){
            // there must already be an existing BBRef
            oa::oaModBitNet *net = multiRef.net;
            assert(net);
            assert(net->getAppDefs().includes(bbRefAppDef));
            multiRef.bb = bbRefAppDef->get(net);
            multiRef.type = BBREF;
        }

        assert(multiRef.type == BBREF);
 
        // setup one input of this operator
        driverBBRefs1.push_back(multiRef.bb);
    }
    vector<BBRef> driverBBRefsSel;
    for(multiRefIter = select.begin(); multiRefIter != select.end(); ++ multiRefIter){

        MultiRef multiRef = *multiRefIter;

        if(multiRef.type == NET){
            // there must already be an existing BBRef
            oa::oaModBitNet *net = multiRef.net;
            assert(net);
            assert(net->getAppDefs().includes(bbRefAppDef));
            multiRef.bb = bbRefAppDef->get(net);
            multiRef.type = BBREF;
        }

        assert(multiRef.type == BBREF);
 
        // setup one input of this operator
        driverBBRefsSel.push_back(multiRef.bb);
    }

    // create a BB node
    return MultiRef(currentManager->bbg.busMux(driverBBRefs1, driverBBRefsSel));

}



// *****************************************************************************
// mux()
//
//
// *****************************************************************************
void
Synthesis::mux(MultiRefBus &result, MultiRefBus& select, 
        MultiRefBus &in0, MultiRefBus &in1) {
    assert(in0.size() == in1.size());
    result.clear();

    // have we created a functional manager for this design yet?
    if (currentManager == NULL) {
        currentManager = Manager::get(currentModule->getDesign());
    }
    
    MultiRefBus::iterator multiRefIter;
    vector<BBRef> driverBBRefs1;
    for(multiRefIter = in0.begin(); multiRefIter != in0.end(); ++ multiRefIter){

        MultiRef multiRef = *multiRefIter;

        if(multiRef.type == NET){
            // there must already be an existing BBRef
            oa::oaModBitNet *net = multiRef.net;
            assert(net);
            assert(net->getAppDefs().includes(bbRefAppDef));
            multiRef.bb = bbRefAppDef->get(net);
            multiRef.type = BBREF;
        }

        assert(multiRef.type == BBREF);
 
        // setup one input of this operator
        driverBBRefs1.push_back(multiRef.bb);
    }
    vector<BBRef> driverBBRefs2;
    for(multiRefIter = in1.begin(); multiRefIter != in1.end(); ++ multiRefIter){

        MultiRef multiRef = *multiRefIter;

        if(multiRef.type == NET){
            // there must already be an existing BBRef
            oa::oaModBitNet *net = multiRef.net;
            assert(net);
            assert(net->getAppDefs().includes(bbRefAppDef));
            multiRef.bb = bbRefAppDef->get(net);
            multiRef.type = BBREF;
        }

        assert(multiRef.type == BBREF);
 
        // setup one input of this operator
        driverBBRefs2.push_back(multiRef.bb);
    }
    vector<BBRef> driverBBRefsSel;
    for(multiRefIter = select.begin(); multiRefIter != select.end(); ++ multiRefIter){

        MultiRef multiRef = *multiRefIter;

        if(multiRef.type == NET){
            // there must already be an existing BBRef
            oa::oaModBitNet *net = multiRef.net;
            assert(net);
            assert(net->getAppDefs().includes(bbRefAppDef));
            multiRef.bb = bbRefAppDef->get(net);
            multiRef.type = BBREF;
        }

        assert(multiRef.type == BBREF);
 
        // setup one input of this operator
        driverBBRefsSel.push_back(multiRef.bb);
    }

    // create a BB node
    vector<BBRef> outputBBRefs;
    currentManager->bbg.busMux(driverBBRefs1, driverBBRefs2, driverBBRefsSel,
            outputBBRefs);

    // setup outputs (result)
    vector<BBRef>::iterator bbRefIter;
    for(bbRefIter = outputBBRefs.begin(); bbRefIter != outputBBRefs.end();
            ++ bbRefIter) {
        result.push_front(MultiRef(*bbRefIter));
    }

}


/*
// *****************************************************************************
// fullAdder()
//
//
// *****************************************************************************
void
Synthesis::fullAdder(MultiRef &sum, MultiRef &carryOut, 
                     MultiRef e1, MultiRef e2, MultiRef carryIn) {
    // YH: fullAdder() needs to be updated
    MultiRef intermediate = xorOf(e1, e2);
    sum = xorOf(carryIn, intermediate);
    carryOut = orOf(andOf(e1,e2), andOf(intermediate, carryIn));
}*/


// *****************************************************************************
// multiBitConstant()
//
//
// *****************************************************************************
void
Synthesis::multiBitConstant(MultiRefBus &result, int value, int bits) {
    result.clear();
    for(int i=0; (bits == 0 ? value != 0 : i<bits); i++, value = value >> 1) {
        if (value % 2) {
            result.push_front(constantOne());
        } else {
            result.push_front(constantZero());
        }
    }
    if (result.empty()) {
        result.push_back(constantZero());
    }
}

}

---