oagFpga.h File Reference

#include "oaDesignDB.h"
#include "oagFpgaObserver.h"
#include "oagFpgaDebug.h"
#include "oagFpga.h"
#include <list>

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Namespaces
namespace	oagFpga
Reading and writing functional descriptions from other formats
void	writeVerilog (oa::oaLib *library, oa::oaView *view, const char *filename)
	Write an OpenAccess library (and functional descriptions) to a Verilog file.
void	writeVerilog (oa::oaDesign *design, const char *filename)
	Write an OpenAccess design (and functional description) to a Verilog file.
oa::oaModBitNet *	toBitNet (oa::oaModNet *net)
Defines
#define	oagFpga_P

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Define Documentation

#define oagFpga_P

Definition at line 3 of file oagFpga.h.

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Function Documentation

oa::oaModBitNet* toBitNet (  oa::oaModNet *  net  )  [inline]

If the given net has multiple bits, an assertion will be generated. Definition at line 87 of file oagFpga.h. Referenced by oagFpga::ModGraph::connectEquivalentNetsInGraph(), oagFpga::AiModGraph::connectEquivalentNetsInGraph(), oagFpga::OccGraph::getAllConnections(), oagFpga::OccGraph::getInputs(), oagFpga::AiModGraph::getInputs(), oagFpga::OccGraph::getNetToBBConnection(), oagFpga::OccGraph::getOutputs(), oagFpga::ModGraph::getOutputs(), oagFpga::AiModGraph::getOutputs(), oagFpga::MapperUtils::identifyControls(), oagFpga::MapperUtils::mergeEquivalentNets(), oagFpga::Manager::print(), oagFpga::MapperUtils::removeDanglingNets(), and oagFpga::writeVerilog().

void oagFpga::writeVerilog (  oa::oaDesign *  design, const char *  filename )

Write an OpenAccess design (and functional description) to a Verilog file. The Verilog description will be appended to the end of the file. Modules, instances, scalar nets, bus nets, and ports/terminals are mapped directly from OpenAccess database objects to Verilog Nets which are undriven by a signal but marked equivalent (through the OpenAccess markEquivalent method) to another net that is driven by a signal will be assigned using a direct Verilog "assign" All BB and TERMINAL nodes are mapped to new Verilog nets names "bb_XXX" where XXX is the Ref of the node. The functionality is described using primivtive instantiation, one per BB node If there are pre-existing OpenAccess nets of a conflicting name "bb_XXX", an error will be generated. Parameters: design  filename  Definition at line 320 of file oagFpgaVerilogWriter.cpp. References oagFpga::BBRef, oagFpga::getBaseName(), oagFpga::ModRef::ref, oagFpga::refToVerilogName(), oagFpga::toBitNet(), oagFpga::writeBBNodeToVerilog(), and oagFpga::writeNetDef(). Referenced by oagFpga::writeVerilog().

void oagFpga::writeVerilog (  oa::oaLib *  lib, oa::oaView *  view, const char *  filename )

Write an OpenAccess library (and functional descriptions) to a Verilog file. The Verilog descriptions will be appended to the end of the file. Parameters: lib  filename  Definition at line 605 of file oagFpgaVerilogWriter.cpp. References oagFpga::writePrimitiveBlackBoxs(), and oagFpga::writeVerilog().

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