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oagFpgaMapperUtils.h

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00001 
00002 #if !defined(oagMapperUtils_P)
00003 #define oagMapperUtils_P
00004 
00005 #include "oaDesignDB.h"
00006 #include "oagFpga.h"
00007 #include "oagFpgaAiModGraph.h"
00008 #include "oagFpgaAiModRef.h"
00009 #include <list>
00010 
00011 using namespace std;
00012 
00013 namespace oagFpga {
00014 
00015 // *****************************************************************************
00016 // MapUtils
00017 //
00019 //
00020 // *****************************************************************************
00021 
00022 class MapperUtils {
00023   friend class FpgaMapper;
00024 
00025   public:
00026   
00027     MapperUtils();
00028 
00029     typedef enum{POSEDGE, NEGEDGE} TriggerType;
00030 
00033                
00034     void                printGateUsage(oa::oaModule *target);
00035        
00039 
00040     void                mergeEquivalentNets(oa::oaModule *module);
00041     void                removeDanglingNets(oa::oaModule *module);
00042     
00046 
00047     // for sequential gate
00048     oa::oaDesign       *seqGate;
00049     oa::oaModTerm      *seqInput, *seqOutput;
00050     oa::oaModTerm      *seqReset, *seqPreset, *seqClock;
00051     TriggerType         seqResetTrigger, seqPresetTrigger, seqClockTrigger;
00052 
00053     // for LUT
00054     oa::oaDesign               *lutGate;
00055     vector<oa::oaModTerm *>     lutInputs;
00056     oa::oaModTerm              *lutOutput;
00057 
00058     // delay and area cost for technology cells
00059     float               seqArea, seqDelay;
00060     float               lutArea, lutDelay;
00061 
00065     
00066   public:
00067     oa::oaDesign *      createSeq(oa::oaLib* curLib, oa::oaView* curView);
00068     oa::oaDesign *      createLut(oa::oaLib* curLib, oa::oaView* curView, int K);
00069 
00070     void                setSeq(oa::oaDesign *gate) { seqGate = gate; }
00071     void                setLut(oa::oaDesign *gate) { lutGate = gate; }
00072 
00073     oa::oaDesign *      getLut() { return lutGate; }
00074     oa::oaDesign *      getSeq() { return seqGate; }
00075 
00079     
00080     void                addGlobalClock(oa::oaModBitNet *clock, const TriggerType trig = POSEDGE) {
00084       if (trig == POSEDGE) posClocks.insert(clock); else negClocks.insert(clock);
00085     }
00086     void                addGlobalReset(oa::oaModBitNet *reset, const TriggerType trig = POSEDGE) {
00090       if (trig == POSEDGE) posAsyncResets.insert(reset); else negAsyncResets.insert(reset);
00091     }
00092     void                identifyControls(oa::oaModule *module);
00093     void                identifyControls(AiModRef seq);
00094     void                removeAsyncResetsFromLogic(oa::oaModule *module);
00095 
00096 #ifdef CELL_MAPPING
00097     void                connectAllControls(AiModRef ref, oa::oaModInst *inst);
00098 #endif // #ifdef CELL_MAPPING 
00099 
00100   protected:
00101 
00102     set<oa::oaModBitNet*>     posAsyncResets, negAsyncResets; 
00103     set<oa::oaModBitNet*>     posClocks, negClocks;
00104     
00105 #ifdef CELL_MAPPING
00106     void                      connectControl(oa::oaModTerm *term, 
00107                                 oa::oaModInst *inst,
00108                                 oa::oaModBitNet *net,
00109                                 bool inverted = false);
00110 #endif // #ifdef CELL_MAPPING 
00111 
00113 
00114 };
00115 
00116 }
00117 #endif

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