oagFpga::FpgaMapper Class Reference
A cut-based mapper.
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#include <oagFpgaMapper.h>
Collaboration diagram for oagFpga::FpgaMapper:
[legend]List of all members.
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Main mapping routines |
| | FpgaMapper (int cutsPerNode) |
| void | techmapDelay (oa::oaModule *target) |
| void | techmapArea (oa::oaModule *target) |
| MapperUtils | mapUtils |
Simulation and matching |
| void | addTrivialGates () |
| void | initializeSimulation () |
| void | simulate (oa::oaDesign *design, TableEntry &outResult, AiModRef &out, vector< AiModRef > cut) |
| int | cutsPerNode |
| unsigned int | exhaustiveInputVectors [MAX_CUT_SIZE][TableEntry::MAX_WORDS] |
Intermediate Mapping State |
| double | getCumulativeAreaCost (AiModGraph::Cut *cut, TableEntry *choice) |
| double | getCumulativeDelayCost (AiModGraph::Cut *cut, TableEntry *choice) |
| map< AiModRef, TableEntry * > | choice_p |
| map< AiModRef, TableEntry * > | choice_n |
| map< AiModRef, AiModGraph::Cut > | cut_p |
| map< AiModRef, AiModGraph::Cut > | cut_n |
| map< AiModRef, double > | cost_p |
| map< AiModRef, double > | cost_n |
| map< AiModRef, oa::oaModBitNet * > | mapped |
| double | totalArea |
| double | totalDelay |
| int | gateCount |
| int | seqCount |
Library information |
| void | setAreaCosts () |
| void | setDelayCosts () |
| TableEntry | notEntry |
| TableEntry | constantZeroEntry |
Public Types |
| enum | TriggerType { POSEDGE,
NEGEDGE
} |
Protected Member Functions |
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| void | implementAll (oa::oaModule *target) |
| oa::oaModInst * | implementSeqNode (AiModRef x) |
| oa::oaModBitNet * | implementNode (AiModRef x) |
Detailed Description
A cut-based mapper.
Implements the abstract functionality inside of a module using a set of concrete library cells. The matching is Boolean and cut-based and is accomplished by generating and matching exhaustive truth-tables for the library gates and for small slices of the target design.
First, a set of library cells need to be provided through the addLibraryGate method. These cells should be (i) combinational (ii) have a single output (iii) have at most MAX_CUT_SIZE inputs each. One of the cells must also be an inverter (it will be detected automatically).
Once the library is initialized, the target design can be mapped using one the available techmap() routines.
If the design had any pre-existing hierarchy, it will be left untouched. Only abstract functionality implemented within this module itself will be mapped. If this is not the desired behavior, consider flattening the design first (i.e. oagFpga::collapseAllInstancesAllLevels()).
Definition at line 40 of file oagFpgaMapper.h.
Member Enumeration Documentation
Constructor & Destructor Documentation
| oagFpga::FpgaMapper::FpgaMapper |
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int |
cutsPerNode |
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Member Function Documentation
| void oagFpga::FpgaMapper::addTrivialGates |
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[protected] |
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| double oagFpga::FpgaMapper::getCumulativeAreaCost |
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AiModGraph::Cut * |
cut, |
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TableEntry * |
choice |
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) |
[protected] |
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| double oagFpga::FpgaMapper::getCumulativeDelayCost |
( |
AiModGraph::Cut * |
cut, |
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TableEntry * |
choice |
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) |
[protected] |
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| void oagFpga::FpgaMapper::implementAll |
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oa::oaModule * |
target |
) |
[protected] |
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| oa::oaModBitNet* oagFpga::FpgaMapper::implementNode |
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AiModRef |
x |
) |
[protected] |
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| oa::oaModInst* oagFpga::FpgaMapper::implementSeqNode |
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AiModRef |
x |
) |
[protected] |
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| void oagFpga::FpgaMapper::initializeSimulation |
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[protected] |
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| void oagFpga::FpgaMapper::setAreaCosts |
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[protected] |
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| void oagFpga::FpgaMapper::setDelayCosts |
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[protected] |
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| void oagFpga::FpgaMapper::simulate |
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oa::oaDesign * |
design, |
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TableEntry & |
outResult, |
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AiModRef & |
out, |
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vector< AiModRef > |
cut |
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) |
[protected] |
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| void oagFpga::FpgaMapper::techmapArea |
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oa::oaModule * |
target |
) |
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| void oagFpga::FpgaMapper::techmapDelay |
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oa::oaModule * |
target |
) |
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Member Data Documentation
The documentation for this class was generated from the following file:
Generated on Mon Jul 9 14:17:22 2007 for OA Gear Fpga by
1.3.9.1