#include <oagFpgaMapperUtils.h>
Mapping sequential signals | |
void | addGlobalClock (oa::oaModBitNet *clock, const TriggerType trig=POSEDGE) |
void | addGlobalReset (oa::oaModBitNet *reset, const TriggerType trig=POSEDGE) |
Manually identifies a net as a global clock. | |
void | identifyControls (oa::oaModule *module) |
Attempts to identify the control signals of all sequential gates in a module. | |
void | identifyControls (AiModRef seq) |
Attempts to identify the control signals of a sequential node as resets, clocks, etc. | |
void | removeAsyncResetsFromLogic (oa::oaModule *module) |
Removes sequential control signals from logic. | |
set< oa::oaModBitNet * > | posAsyncResets |
set< oa::oaModBitNet * > | negAsyncResets |
set< oa::oaModBitNet * > | posClocks |
set< oa::oaModBitNet * > | negClocks |
Public Types | |
enum | TriggerType { POSEDGE, NEGEDGE } |
Public Member Functions | |
MapperUtils () | |
Constructor. | |
Informational queries | |
void | printGateUsage (oa::oaModule *target) |
Prints the number of times each gate is used as an instance. | |
Structural clean-up operations | |
void | mergeEquivalentNets (oa::oaModule *module) |
Replaces all groups of equivalent nets with a single net. | |
void | removeDanglingNets (oa::oaModule *module) |
Removes all the nets in a module that are not connected to either an Inst or a port. | |
create modules for these two types of library cells | |
oa::oaDesign * | createSeq (oa::oaLib *curLib, oa::oaView *curView) |
Create a design with top module as a sequential element. | |
oa::oaDesign * | createLut (oa::oaLib *curLib, oa::oaView *curView, int K) |
Create a design with top module as a LUT element. | |
void | setSeq (oa::oaDesign *gate) |
void | setLut (oa::oaDesign *gate) |
oa::oaDesign * | getLut () |
oa::oaDesign * | getSeq () |
Public Attributes | |
Important library cells | |
oa::oaDesign * | seqGate |
oa::oaModTerm * | seqInput |
oa::oaModTerm * | seqOutput |
oa::oaModTerm * | seqReset |
oa::oaModTerm * | seqPreset |
oa::oaModTerm * | seqClock |
TriggerType | seqResetTrigger |
TriggerType | seqPresetTrigger |
TriggerType | seqClockTrigger |
oa::oaDesign * | lutGate |
vector< oa::oaModTerm * > | lutInputs |
oa::oaModTerm * | lutOutput |
float | seqArea |
float | seqDelay |
float | lutArea |
float | lutDelay |
Friends | |
class | FpgaMapper |
Definition at line 22 of file oagFpgaMapperUtils.h.
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Definition at line 29 of file oagFpgaMapperUtils.h. |
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Constructor.
Definition at line 25 of file oagFpgaMapperUtils.cpp. References lutGate, lutOutput, seqClock, seqGate, seqInput, seqOutput, seqPreset, and seqReset. |
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Definition at line 80 of file oagFpgaMapperUtils.h. Referenced by oagFpga::lutMap(). |
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Manually identifies a net as a global clock.
Definition at line 86 of file oagFpgaMapperUtils.h. Referenced by oagFpga::lutMap(). |
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Create a design with top module as a LUT element. The created K-LUT element includes the following terminals: K inputs and an Output. Definition at line 143 of file oagFpgaMapperUtils.cpp. References lutGate, lutInputs, and lutOutput. Referenced by oagFpga::lutMap(). |
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Create a design with top module as a sequential element. The created sequential element includes the following terminals: Data, Clock, Preset, Reset and Output. Definition at line 44 of file oagFpgaMapperUtils.cpp. References seqClock, seqClockTrigger, seqGate, seqInput, seqOutput, seqPreset, seqPresetTrigger, seqReset, and seqResetTrigger. Referenced by oagFpga::lutMap(). |
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Definition at line 73 of file oagFpgaMapperUtils.h. |
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Definition at line 74 of file oagFpgaMapperUtils.h. |
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Attempts to identify the control signals of a sequential node as resets, clocks, etc.
Definition at line 309 of file oagFpgaMapperUtils.cpp. References DEBUG_PRINTLN, oagFpga::AiModRef::module, negAsyncResets, negClocks, posAsyncResets, posClocks, and oagFpga::toBitNet(). |
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Attempts to identify the control signals of all sequential gates in a module.
Definition at line 291 of file oagFpgaMapperUtils.cpp. |
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Replaces all groups of equivalent nets with a single net.
Definition at line 632 of file oagFpgaMapperUtils.cpp. References oagFpga::toBitNet(). |
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Prints the number of times each gate is used as an instance. Unimplemented. Definition at line 703 of file oagFpgaMapperUtils.cpp. Referenced by oagFpga::lutMap(). |
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Removes sequential control signals from logic. All sequential control signals are synthesized in a very general manner. They are added as generic triggers on a sequential node, and any additional functional behavior is implemented in logic surrounding the sequential node. Two common examples of this are asynchronous resets and presets. These are triggers, but also affect the function being latched (i.e. the '0' function will be latched on an asynchronous reset and the '1' function will be latched on an asynchronous preset). In library gates that have asynchronous resets and presets, these inputs will both trigger the gate and set its state to the appropriate value. There is no need to keep the logic on the input of the sequential element that had previously driven the next state input to the appropriate reset values. In fact, this logic is entirely useless and may confuse some equivalence checkers. This function removes the asynchronous resets and presets from the input logic of sequential elements, replacing them with a constant that reflects the unasserted value of the signal.
Definition at line 251 of file oagFpgaMapperUtils.cpp. References negAsyncResets, and posAsyncResets. |
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Removes all the nets in a module that are not connected to either an Inst or a port. The terminal nodes in the underlying AIG are also removed.
Definition at line 761 of file oagFpgaMapperUtils.cpp. References DEBUG_PRINTLN, and oagFpga::toBitNet(). Referenced by oagFpga::lutMap(). |
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Definition at line 71 of file oagFpgaMapperUtils.h. |
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Definition at line 70 of file oagFpgaMapperUtils.h. |
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Definition at line 23 of file oagFpgaMapperUtils.h. |
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Definition at line 60 of file oagFpgaMapperUtils.h. |
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Definition at line 60 of file oagFpgaMapperUtils.h. |
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Definition at line 54 of file oagFpgaMapperUtils.h. Referenced by createLut(), and MapperUtils(). |
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Definition at line 55 of file oagFpgaMapperUtils.h. Referenced by createLut(). |
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Definition at line 56 of file oagFpgaMapperUtils.h. Referenced by createLut(), and MapperUtils(). |
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Definition at line 102 of file oagFpgaMapperUtils.h. Referenced by identifyControls(), and removeAsyncResetsFromLogic(). |
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Definition at line 103 of file oagFpgaMapperUtils.h. Referenced by identifyControls(). |
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Definition at line 102 of file oagFpgaMapperUtils.h. Referenced by identifyControls(), and removeAsyncResetsFromLogic(). |
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Definition at line 103 of file oagFpgaMapperUtils.h. Referenced by identifyControls(). |
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Definition at line 59 of file oagFpgaMapperUtils.h. |
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Definition at line 50 of file oagFpgaMapperUtils.h. Referenced by createSeq(), and MapperUtils(). |
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Definition at line 51 of file oagFpgaMapperUtils.h. Referenced by createSeq(). |
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Definition at line 59 of file oagFpgaMapperUtils.h. |
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Definition at line 48 of file oagFpgaMapperUtils.h. Referenced by createSeq(), and MapperUtils(). |
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Definition at line 49 of file oagFpgaMapperUtils.h. Referenced by createSeq(), and MapperUtils(). |
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Definition at line 49 of file oagFpgaMapperUtils.h. Referenced by createSeq(), and MapperUtils(). |
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Definition at line 50 of file oagFpgaMapperUtils.h. Referenced by createSeq(), and MapperUtils(). |
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Definition at line 51 of file oagFpgaMapperUtils.h. Referenced by createSeq(). |
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Definition at line 50 of file oagFpgaMapperUtils.h. Referenced by createSeq(), and MapperUtils(). |
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Definition at line 51 of file oagFpgaMapperUtils.h. Referenced by createSeq(). |