oagFpgaMapper.h

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#if !defined(oagFpgaMapperTable_P)
#define oagFpgaMapperTable_P

#include "oaDesignDB.h"
#include "oagFpga.h"
#include "oagFpgaAiModGraph.h"
#include "oagFpgaMapperUtils.h"
#include <map>

using namespace std;

namespace oagFpga {

// *****************************************************************************
// FpgaMapper
//
// *****************************************************************************

    class FpgaMapper {

        static const int MAX_CUT_SIZE = 4;

        struct TableEntry {
            static const unsigned int MAX_WORDS = 1;
            // MAX_WORDS should be consistent with MAX_CUT_SIZE
            // basically 2^MAX_CUT_SIZE = 32*MAX_WORDS
            static const unsigned int BITS_PER_WORD = sizeof(unsigned int)*8;

            unsigned int         func[MAX_WORDS];

            inline void setBit(unsigned int bit, bool val) {
                assert(bit/32 < MAX_WORDS);
                func[bit/32] &= ~(0x1 << (bit%32)); // clear always
                func[bit/32] |= ((val & 0x1) << (bit%32)); // set appropriately
            }
            inline bool getBit(unsigned int bit) {
                assert(bit/32 < MAX_WORDS);
                return (func[bit/32] >> (bit%32)) & 0x1;
            }

            // NOTE: there is no need to have N_input for LUT based map,
            // i keep it at present due to the reason that i'm too lazy to 
            // remove all its correspondat stuffs...
            unsigned char   N_input;      // bitfield of input inversions

#ifdef CELL_MAPPING
            unsigned char   directInput;  // input number of direct connection
            unsigned char   directFlag;   // bit flag of direct connection
            unsigned char   constantFlag; // bit flag of constant function
            unsigned char   P;            // permutation ID of inputs
            oa::oaDesign   *cell;           // where the functional description lies
            oa::oaDesign   *implementCell;  // the cell to actually be implemented
#else
            // For LUT based mapping, i assume that the implementation cells 
            // for all TableEntry are LUTs.
            // TODO: to extend the mapper to consider multiple types of LUTs, 
            // "implementCell" can be used

#endif // #ifdef CELL_MAPPING

            float           cost;

            TableEntry() { 
                N_input = 0; 
#ifdef CELL_MAPPING
                cell = NULL; 
#else
                // NOTE: i initiliaze the cost of the TableEntry as 1.0 which is 
                // both area and delay cost of a LUT.
                // TODO: extra routines need to be written for general cost
                cost = 1.0; 
                // none of inputs in a LUT is inverted
                bzero(&N_input, sizeof(unsigned char));
#endif

            }
            TableEntry(const TableEntry &copy) { memcpy(this, &copy, sizeof(TableEntry)); }

            inline bool match(const TableEntry & t) {
                for(unsigned int i=0;i<MAX_WORDS;i++) {
                    if (func[i] != t.func[i]) {
                        return false;
                    }
                }
                return true;
            }
        };

    public:

        typedef enum{POSEDGE, NEGEDGE} TriggerType;


        FpgaMapper(int cutsPerNode);

#ifdef CELL_MAPPING
        void                useAlternateView(const oa::oaScalarName &viewName);
        void                addLibraryGate(oa::oaDesign* design);
#endif // #ifdef CELL_MAPPING

        void                techmapDelay(oa::oaModule *target);
        void                techmapArea(oa::oaModule *target);

        MapperUtils    mapUtils;

    protected:


        void                     addTrivialGates();

        int                      cutsPerNode;

#ifdef CELL_MAPPING
        std::vector<TableEntry>  tables[MAX_CUT_SIZE+1];
#endif //#ifdef CELL_MAPPING

        void                     initializeSimulation();
        void                     simulate(oa::oaDesign *design,
                                    TableEntry &outResult, AiModRef & out, 
                                    vector<AiModRef> cut);
        unsigned int             exhaustiveInputVectors[MAX_CUT_SIZE][TableEntry::MAX_WORDS];




        map<AiModRef,TableEntry *>            choice_p, choice_n;
        map<AiModRef,AiModGraph::Cut>           cut_p, cut_n;
        map<AiModRef,double>                  cost_p, cost_n;
        map<AiModRef,oa::oaModBitNet*>        mapped;

        double     totalArea, totalDelay;
        int        gateCount;
        int        seqCount;

        double getCumulativeAreaCost(AiModGraph::Cut *cut, TableEntry *choice);
        double getCumulativeDelayCost(AiModGraph::Cut *cut, TableEntry *choice);

    protected:

        void                implementAll(oa::oaModule *target);
        oa::oaModInst *     implementSeqNode(AiModRef x);
        oa::oaModBitNet *   implementNode(AiModRef x);

#ifdef CELL_MAPPING
        std::list<oa::oaDesign*> libraryCells;
        oa::oaScalarName         alternateViewName;
        bool                     useAlternateViews;
        TableEntry              *notEntry;
#else
        TableEntry              notEntry;
        TableEntry              constantZeroEntry;

#endif // #ifdef CELL_MAPPING

        void   setAreaCosts();
        void   setDelayCosts();


    };

}
#endif

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