Simultaneous Floorplanning and Synthesis for FPGA (by Yu Hu, 09/24/07)

1. Layout-Driven Synthesis
1. William E. Dougherty and Donald E. Thomas, Unifying Behavioral Synthesis and Physical Design, DAC 2000.
2. Min Xu and Fadi Kurdahi, Layout-Driven High Level Synthesis for FPGA Based Architectures, DATE 1998.
3. Shanntanu Tarafdar, Mirjam Leeser and Zixin Yin, Integrating Floorplanning In Data-Transfer Based High-Level Synthesis, ICCAD 1998.

2. FPGA Floorplanning and Placement
1. Lei Cheng and Martin Wong, Floorplan Design for Multi-Million Gate FPGAs, ICCAD 2004. [ppt]
2. Joh Emmert, Akash Randhar and Dinesh Bhatia, Fast Ploorplanning for FPGAs, FPL 1998.
3. Joh Emmert and Dinesh Bhatia, A Methodology for Fast FPGA Floorplanning, FPGA 1999.
4. Russel Tessier, Fast Placement Approaches for FPGAs, TOADES 2002.
5. Joh Emmert and Dinesh Bhatia, Two-Dimensional Placement Using Tabu Search, Journal of VLSI, 1999.