oagFpga.cpp

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#include "oaDesignDB.h"
#include "oagFpga.h"
#include "oagFpgaManager.h"
#include "oagFpgaMapper.h"
//#include "oagFpgaTimingLibrarySynthesis.h"
#include "oagFpgaVerilogSynthesis.h"
//#include "oagFpgaModGraph.h"
//#include "oagFpgaOccGraph.h"
#include "oagFpgaModuleCompiler.h"
#include <iostream>

#include "oagFpgaDebug.h"

// *****************************************************************************
// Global static variable definitions.
// *****************************************************************************

extern char                          *oagFpgaVerilog_yyfilename;
extern FILE                          *oagFpgaVerilog_yyin;
int                                   oagFpgaVerilog_yyparse();
extern oagFpga::VerilogDesign        *oagFpgaVerilog_yydesign;
extern FILE                          *oagFpgaLib_yyin;
int                                   oagFpgaLib_yyparse();

namespace oagFpga {

// *****************************************************************************
// Class static variable definitions.
// *****************************************************************************

//  application extension (for each design) for read/save the additional information
oa::oaVarDataAppDef<oa::oaDesign>           *streamAppDef;
//  application extension (for each design) for Manager class
oa::oaVoidPointerAppDef<oa::oaDesign>       *managerAppDef;
//  application extension (for each net) for connecting net and black box graph
oa::oaIntAppDef<oa::oaModBitNet>            *bbRefAppDef;
//  application extension (for each net) for connecting net and AIG
oa::oaIntAppDef<oa::oaModBitNet>            *AiRefAppDef;
    
Observer                                    *observer;

using namespace std;


// *****************************************************************************
// initialize()
//
//
// *****************************************************************************
void            
initialize() {
    streamAppDef = 
        oa::oaVarDataAppDef<oa::oaDesign>::get(oa::oaString("oagFpga_function_stream"));
    managerAppDef = 
        oa::oaVoidPointerAppDef<oa::oaDesign>::get(oa::oaString("oagFpga_manager"));
    bbRefAppDef =
        oa::oaIntAppDef<oa::oaModBitNet>::get(oa::oaString("oagFpga_RTLGraphRef"));
    AiRefAppDef =
        oa::oaIntAppDef<oa::oaModBitNet>::get(oa::oaString("oagAi_Graph"));

    observer = new Observer();
}


// *****************************************************************************
// readVerilog()
//
//
// *****************************************************************************
void
readVerilog(oa::oaLib *library, const char *filename) {
    assert(library);
    assert(filename);

    oa::oaNativeNS nativeNS;
    oa::oaScalarName viewName(nativeNS, "netlist");

    // read Verilog
    readVerilog(library, viewName, filename);
}


// *****************************************************************************
// readVerilog()
//
//
// *****************************************************************************
void
readVerilog(oa::oaLib *library, const oa::oaScalarName &viewName, 
        const char *filename) {
    assert(library);
    assert(filename);

    if(library->getAccess(oa::oaLibAccess(oa::oacWriteLibAccess))) {
        const oa::oaViewType *viewType = oa::oaViewType::get(oa::oacNetlist);
        oa::oaView *view = oa::oaView::get(library, viewName, viewType);
        assert(view);

        // parse verilog file
        VerilogSynthesis::setLibrary(library);
        VerilogSynthesis::setView(view);
        oagFpgaVerilog_yyfilename = const_cast<char *>(filename);
        oagFpgaVerilog_yyin = fopen(filename, "r");
        if (!oagFpgaVerilog_yyin) {
            cerr << "ERROR: Could not open Verilog file " << filename << endl;
            exit(0);
        }

        cerr << "Begin to parse Verilog file, please wait..." << endl;

        oagFpgaVerilog_yyparse();

        cerr << "Parsing is done!" << endl;

        cerr << "Begin to synthesize Verilog modules, please wait..." << endl;

        VerilogSynthesis::synthesize(oagFpgaVerilog_yydesign);

        cerr << "Begin to perform module compiler, please wait..." << endl;

        ModuleCompiler::compileModules(library, view);

        cerr << "Synthesis is done!" << endl;

        fclose(oagFpgaVerilog_yyin);

        library->releaseAccess();
    } else {
        cerr << "ERROR: Could not write into library " << endl;
        exit(0);
    }
}

#ifdef YU_TEST

oa::oaLib* YuTestCurLib;
oa::oaView* YuTestCurView;


void YuTest(oa::oaLib* curLib, oa::oaView* curView, oa::oaModule* currentModule) {
    const oa::oaNativeNS nativeNS;
    const oa::oaScalarName cellName(nativeNS, "MYLUT");
    oa::oaScalarName    libName;
    curLib->getName(libName);
    oa::oaScalarName    viewName;
    curView->getName(viewName);

    oa::oaDesign* lutDesign = oa::oaDesign::open(libName, cellName, 
        viewName, oa::oaViewType::get(oa::oacNetlist), 'w');
    oa::oaModule* lutModule = oa::oaModule::create(lutDesign, cellName); 
    lutDesign->setTopModule(lutModule );

    oa::oaModScalarInst *inst = oa::oaModScalarInst::create(currentModule, lutDesign);
    cerr << "LUT instant is created!" << endl;
    exit(0);
}



#endif // ifdef YU_TEST


// *****************************************************************************
// lutMap()
//
//
// *****************************************************************************
void lutMap(oa::oaLib* curLib, oa::oaView* curView,
             oa::oaDesign *targetDesign,
             int lutSize = 4,
             int cutsPerNode = 200, 
             bool flatten = false, 
             char* clockNetName = NULL,
             char* clockTriggerName = NULL,
             char* resetNetName = NULL,
             char* resetTriggerName = NULL,
             char* objectiveName = "area"
             ) 
{

//    int lutSize = 4;
//    int cutsPerNode = 200;
//    bool flatten = false; 
//    char* clockNetName = NULL;
//    char* clockTriggerName = NULL;
//    char* resetNetName = NULL;
//    char* resetTriggerName = NULL;
//    char* objectiveName = "delay";

#ifdef YU_TEST
    YuTestCurLib = curLib;
    YuTestCurView = curView;
#endif // #ifdef YU_TEST

    const oa::oaVerilogNS verilogNS;

    // initialize mapper
    FpgaMapper mapper(cutsPerNode);
    mapper.mapUtils.createSeq(curLib, curView);
    mapper.mapUtils.createLut(curLib, curView, lutSize);
    // TODO: mapper.useAlternateView(instanceViewName);

    // Flatten
    if (flatten) {
        cerr << "Flattening is currently not implemented." << endl;
        QUIT_ON_INTERNAL_ERROR;
        //cout << "Flattening \'" << cellString << "\' ... " << endl;
        //oagFunc::collapseAllInstancesAllLevels(targetDesign->getTopModule());
    }

    // Manually identify clocks/resets
    if (clockNetName) {
        oa::oaScalarName clockName(verilogNS, clockNetName);
        oa::oaModNet *clockNet = oa::oaModNet::find(targetDesign->getTopModule(), clockName);
        if (!clockNet) {
            cerr << "ERROR: Could not find clock net: " << clockNet << endl;
            exit(0);
        }
        if (clockNet->getNumBits() != 1) {
            cerr << "ERROR: Clock net not a single bit net: " << clockNet << endl;
            exit(0);                
        }
        MapperUtils::TriggerType clockTrigger = MapperUtils::POSEDGE;
        if (clockTrigger) {
            if (!strcmp(static_cast<const char*>(clockTriggerName), "pos")) {
                clockTrigger = MapperUtils::POSEDGE;
            } else if (!strcmp(static_cast<const char*>(clockTriggerName), "neg")) {
                clockTrigger = MapperUtils::NEGEDGE;
            } else {
                cerr << "ERROR: Unknown trigger type.  Use \"pos\" or \"neg\"" << endl;
                exit(0);
            }
        }
        mapper.mapUtils.addGlobalClock(oagFpga::toBitNet(clockNet), clockTrigger);
    }
    if (resetNetName) {
        oa::oaScalarName resetName(verilogNS, resetNetName);
        oa::oaModNet *resetNet = oa::oaModNet::find(targetDesign->getTopModule(), resetName);
        if (!resetNet) {
            cerr << "ERROR: Could not find reset net: " << resetNet << endl;
            exit(0);
        }
        if (resetNet->getNumBits() != 1) {
            cerr << "ERROR: Reset net not a single bit net: " << resetNet << endl;
            exit(0);
        }
        MapperUtils::TriggerType resetTrigger = MapperUtils::POSEDGE;
        if (resetTrigger) {
            if (!strcmp(static_cast<const char*>(resetTriggerName), "pos")) {
                resetTrigger = MapperUtils::POSEDGE;
            } else if (!strcmp(static_cast<const char*>(resetTriggerName), "neg")) {
                resetTrigger = MapperUtils::NEGEDGE;
            } else {
                cerr << "ERROR: Unknown trigger type.  Use \"pos\" or \"neg\"" << endl;
                exit(0);
            }
        }
        mapper.mapUtils.addGlobalReset(oagFpga::toBitNet(resetNet), resetTrigger);
    }

    // Map!
    if (!strcmp(static_cast<const char*>(objectiveName), "area")) {
        mapper.techmapArea(targetDesign->getTopModule());
    } else if (!strcmp(static_cast<const char*>(objectiveName), "delay")) {
        mapper.techmapDelay(targetDesign->getTopModule());
    } else {
        cerr << "ERROR: Can't understand mapping objective.  Try \"area\" or \"delay\"" << endl;
        exit(0);
    }
    mapper.mapUtils.printGateUsage(targetDesign->getTopModule());

    // Remove dangling nets

    mapper.mapUtils.removeDanglingNets(targetDesign->getTopModule());

}

/*
// *****************************************************************************
// readLiberty()
//
//
// *****************************************************************************
void
readLiberty(oa::oaLib *library, const oa::oaScalarName &viewName, const char *filename) {
    assert(library);
    assert(filename);

    if(library->getAccess(oa::oaLibAccess(oa::oacWriteLibAccess))) {
        const oa::oaViewType *viewType = oa::oaViewType::get(oa::oacNetlist);
        oa::oaView *view = oa::oaView::get(library, viewName, viewType);
        assert(view);

        // parse Liberty file
        TimingLibrarySynthesis::initialize();
        TimingLibrarySynthesis::setLibrary(library);
        TimingLibrarySynthesis::setView(view);
        oagFpgaLib_yyin = fopen(filename, "r");
        if (!oagFpgaLib_yyin) {
            cerr << "ERROR: Could not open Liberty file " << filename << endl;
            exit(0);
        }
        cout << "Reading Liberty file " << filename << endl;
        oagFpgaLib_yyparse();
        fclose(oagFpgaLib_yyin);
        library->releaseAccess();
    } else {
        cerr << "ERROR: Could not write into library " << endl;
        exit(0);
    }
}


// *****************************************************************************
// readLiberty()
//
//
// *****************************************************************************
void
readLiberty(oa::oaLib *library, const char *filename) {
    assert(library);
    assert(filename);

    oa::oaNativeNS nativeNS;
    oa::oaScalarName viewName(nativeNS, "netlist");

    // read the Liberty file
    readLiberty(library, viewName, filename);
}


// *****************************************************************************
// findBusTerm()
//
//
// *****************************************************************************
oa::oaOccBusTerm*
findBusTerm(oa::oaOccBusTermBit *bitTerm) {
    assert(bitTerm);

    oa::oaName generalName;
    bitTerm->getName(generalName);
    if (generalName.getScalar()) {
      // ignore scalars
      return NULL;
    }
    assert(generalName.getVectorBit());

    oa::oaOccBusTermDef *busTermDef = static_cast<oa::oaOccBusTermBit*>(bitTerm)->getDef();
    if (busTermDef) {
      oa::oaIter<oa::oaOccBusTerm> busIter(busTermDef->getBusTerms());
      oa::oaOccBusTerm *busTerm = busIter.getNext();
      if (busTerm) {
        return busTerm;
      }
    }
    
    // should never reach this point
    QUIT_ON_INTERNAL_ERROR;
    return NULL;
}


// *****************************************************************************
// findBusNet()
//
//
// *****************************************************************************
oa::oaModBusNet*
findBusNet(oa::oaModBitNet *bitNet) {
    assert(bitNet);

    oa::oaName generalName;
    bitNet->getName(generalName);
    if (generalName.getScalar()) {
      // ignore scalars
      return NULL;
    }
    assert(generalName.getVectorBit());

    oa::oaModBusNetDef *busNetDef = static_cast<oa::oaModBusNetBit*>(bitNet)->getDef();
    if (busNetDef) {
      oa::oaIter<oa::oaModBusNet> busIter(busNetDef->getBusNets());
      oa::oaModBusNet *busNet = busIter.getNext();
      if (busNet) {
        return busNet;
      }
    }
    
    // should never reach this point
    QUIT_ON_INTERNAL_ERROR;
    return NULL;
}
*/

}

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