oagFpga::VerilogDesign::Case Class Reference

A single case inside of a case statement. More...

#include <oagFpgaVerilogDesign.h>

Collaboration diagram for oagFpga::VerilogDesign::Case:

[legend]List of all members.

Public Member Functions
	Case ()
	~Case ()
	Destructor.
Public Attributes
std::list< Expression * > *	conditions
Statement *	action
bool	isDefault

---

Detailed Description

A single case inside of a case statement.

Definition at line 238 of file oagFpgaVerilogDesign.h.

---

Constructor & Destructor Documentation

oagFpga::VerilogDesign::Case::Case (   )  [inline]

Definition at line 244 of file oagFpgaVerilogDesign.h.

oagFpga::VerilogDesign::Case::~Case (   )

Destructor. Definition at line 175 of file oagFpgaVerilogDesign.cpp. References conditions.

---

Member Data Documentation

Statement* oagFpga::VerilogDesign::Case::action

Definition at line 241 of file oagFpgaVerilogDesign.h. Referenced by oagFpga::VerilogSynthesis::synthesizeCase(), and oagFpga::VerilogSynthesis::synthesizeCaseEasy().

std::list<Expression*>* oagFpga::VerilogDesign::Case::conditions

Definition at line 240 of file oagFpgaVerilogDesign.h. Referenced by oagFpga::VerilogSynthesis::synthesizeCase(), oagFpga::VerilogSynthesis::synthesizeCaseEasy(), and ~Case().

bool oagFpga::VerilogDesign::Case::isDefault

Definition at line 242 of file oagFpgaVerilogDesign.h. Referenced by oagFpga::VerilogSynthesis::synthesizeCase(), and oagFpga::VerilogSynthesis::synthesizeCaseEasy().

---

The documentation for this class was generated from the following files:

• oagFpgaVerilogDesign.h
• oagFpgaVerilogDesign.cpp

---