oagFpga::VerilogDesign::Statement Class Reference

A procedural statement. More...

#include <oagFpgaVerilogDesign.h>

Collaboration diagram for oagFpga::VerilogDesign::Statement:

[legend]List of all members.

Public Types
enum	Type {   NOP, BLOCK, IF, CASE,   CASEX, CASEZ, BLOCKING_ASSIGNMENT, NONBLOCKING_ASSIGNMENT }
Public Member Functions
	Statement ()
	~Statement ()
	Destructor.
Public Attributes
Type	type
struct {
Expression *   condition
Statement *   ifTrue
Statement *   ifFalse
std::list< Case * > *   cases
}	ifc
struct {
Expression *   lval
Expression *   rval
}	assign
struct {
std::list< Statement * > *   block
std::list< Declaration * > *   declarations
}	begin_end
std::string	name

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Detailed Description

A procedural statement.

The statement can be one of the following types:

• case
• if / if-else
• blocking assignment
• non-blocking assignment
• begin-end block

Definition at line 263 of file oagFpgaVerilogDesign.h.

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Member Enumeration Documentation

enum oagFpga::VerilogDesign::Statement::Type

Enumeration values: NOP  BLOCK  IF  CASE  CASEX  CASEZ  BLOCKING_ASSIGNMENT  NONBLOCKING_ASSIGNMENT  Definition at line 266 of file oagFpgaVerilogDesign.h.

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Constructor & Destructor Documentation

oagFpga::VerilogDesign::Statement::Statement (   )  [inline]

Definition at line 297 of file oagFpgaVerilogDesign.h. References condition.

oagFpga::VerilogDesign::Statement::~Statement (   )

Destructor. Definition at line 193 of file oagFpgaVerilogDesign.cpp. References assign, begin_end, and ifc.

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Member Data Documentation

struct { ... } oagFpga::VerilogDesign::Statement::assign

Referenced by oagFpga::VerilogSynthesis::synthesizeBlockingassignment(), oagFpga::VerilogSynthesis::synthesizeNonblockingassignment(), and ~Statement().

struct { ... } oagFpga::VerilogDesign::Statement::begin_end

Referenced by oagFpga::VerilogSynthesis::synthesizeBlock(), and ~Statement().

std::list<Statement *>* oagFpga::VerilogDesign::Statement::block

Definition at line 291 of file oagFpgaVerilogDesign.h. Referenced by oagFpga::VerilogSynthesis::synthesizeBlock().

std::list<Case*>* oagFpga::VerilogDesign::Statement::cases

Definition at line 280 of file oagFpgaVerilogDesign.h. Referenced by oagFpga::VerilogSynthesis::synthesizeCase(), and oagFpga::VerilogSynthesis::synthesizeCaseEasy().

Expression* oagFpga::VerilogDesign::Statement::condition

Definition at line 276 of file oagFpgaVerilogDesign.h. Referenced by Statement(), oagFpga::VerilogSynthesis::synthesizeCase(), oagFpga::VerilogSynthesis::synthesizeCaseEasy(), and oagFpga::VerilogSynthesis::synthesizeIf().

std::list<Declaration*>* oagFpga::VerilogDesign::Statement::declarations

Definition at line 292 of file oagFpgaVerilogDesign.h. Referenced by oagFpga::VerilogSynthesis::synthesizeBlock().

struct { ... } oagFpga::VerilogDesign::Statement::ifc

Referenced by oagFpga::VerilogSynthesis::synthesizeCase(), oagFpga::VerilogSynthesis::synthesizeCaseEasy(), oagFpga::VerilogSynthesis::synthesizeIf(), and ~Statement().

Statement* oagFpga::VerilogDesign::Statement::ifFalse

Definition at line 278 of file oagFpgaVerilogDesign.h. Referenced by oagFpga::VerilogSynthesis::synthesizeIf().

Statement* oagFpga::VerilogDesign::Statement::ifTrue

Definition at line 277 of file oagFpgaVerilogDesign.h. Referenced by oagFpga::VerilogSynthesis::synthesizeIf().

Expression* oagFpga::VerilogDesign::Statement::lval

Definition at line 285 of file oagFpgaVerilogDesign.h. Referenced by oagFpga::VerilogSynthesis::synthesizeBlockingassignment(), and oagFpga::VerilogSynthesis::synthesizeNonblockingassignment().

std::string oagFpga::VerilogDesign::Statement::name

Definition at line 295 of file oagFpgaVerilogDesign.h.

Expression* oagFpga::VerilogDesign::Statement::rval

Definition at line 286 of file oagFpgaVerilogDesign.h. Referenced by oagFpga::VerilogSynthesis::synthesizeBlockingassignment(), and oagFpga::VerilogSynthesis::synthesizeNonblockingassignment().

Type oagFpga::VerilogDesign::Statement::type

Definition at line 272 of file oagFpgaVerilogDesign.h. Referenced by oagFpga::VerilogSynthesis::synthesizeBehavioral(), oagFpga::VerilogSynthesis::synthesizeCase(), and oagFpga::VerilogSynthesis::synthesizeCaseEasy().

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The documentation for this class was generated from the following files:

• oagFpgaVerilogDesign.h
• oagFpgaVerilogDesign.cpp

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