oagFpga::VerilogDesign::Instantiation Class Reference

A module instantiation. More...

#include <oagFpgaVerilogDesign.h>

List of all members.

Public Types
enum	PrimitiveType {   ISNT_PRIMITIVE, AND, NAND, OR,   NOR, XOR, XNOR, NOT,   BUF }
Public Member Functions
	Instantiation ()
	~Instantiation ()
	Destructor.
Public Attributes
std::string	name
std::string	type
PrimitiveType	primitive
std::list< Expression * > *	parameters
std::list< PortConnection * > *	connections

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Detailed Description

A module instantiation.

Definition at line 317 of file oagFpgaVerilogDesign.h.

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Member Enumeration Documentation

enum oagFpga::VerilogDesign::Instantiation::PrimitiveType

Enumeration values: ISNT_PRIMITIVE  AND  NAND  OR  NOR  XOR  XNOR  NOT  BUF  Definition at line 322 of file oagFpgaVerilogDesign.h.

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Constructor & Destructor Documentation

oagFpga::VerilogDesign::Instantiation::Instantiation (   )  [inline]

Definition at line 332 of file oagFpgaVerilogDesign.h.

oagFpga::VerilogDesign::Instantiation::~Instantiation (   )

Destructor. Definition at line 229 of file oagFpgaVerilogDesign.cpp. References connections, and parameters.

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Member Data Documentation

std::list<PortConnection*>* oagFpga::VerilogDesign::Instantiation::connections

Definition at line 330 of file oagFpgaVerilogDesign.h. Referenced by oagFpga::VerilogSynthesis::synthesizeModuleInsts(), and ~Instantiation().

std::string oagFpga::VerilogDesign::Instantiation::name

Definition at line 320 of file oagFpgaVerilogDesign.h. Referenced by oagFpga::VerilogSynthesis::synthesizeModuleInsts().

std::list<Expression*>* oagFpga::VerilogDesign::Instantiation::parameters

Definition at line 329 of file oagFpgaVerilogDesign.h. Referenced by oagFpga::VerilogSynthesis::synthesizeModuleInsts(), and ~Instantiation().

PrimitiveType oagFpga::VerilogDesign::Instantiation::primitive

Definition at line 327 of file oagFpgaVerilogDesign.h. Referenced by oagFpga::VerilogSynthesis::synthesizeModuleInsts().

std::string oagFpga::VerilogDesign::Instantiation::type

Definition at line 321 of file oagFpgaVerilogDesign.h. Referenced by oagFpga::VerilogSynthesis::synthesizeModuleInsts().

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The documentation for this class was generated from the following files:

• oagFpgaVerilogDesign.h
• oagFpgaVerilogDesign.cpp

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