Synthesis and Verification for Defect and Soft-error Tolerance
Prof. Lei He
Shi-Jie Wen (Cisco)
C157. Cheng-Ru Chang, Naifeng Jing, Juexiao Su, Shijie Wen, Rich Wong, Lei He , "Heterogeneous Configuration Memory Scrubbing for Soft Error Mitigation in FPGAs", Field-Programmable Technology (FPT), 10-12 Dec. 2012 (pdf)
C149 Zhe Feng, Naifeng Jing, Yu Hu and Lei He, "IPF: In-place X-Filing to Mitigate Soft Errors in SRAM-based FPGAs", International Conference on Field Programmable Logic and Applications(FPL), Sep.,2011.(ppt)(pdf)
C140 Manu Jose, Yu Hu, Rupak Majumdar and Lei He, "Rewiring for Robustness", 47th IEEE Design Automation Conference (DAC'10) , Anaheim, CA, June 13-18, 2010.(pdf)
J44. Yu Hu, Victor Shih, Rupak Majumdar. and Lei He, "Exploiting Symmetries to Speed-Up SAT-Based Boolean Matching for Logic Synthesis of FPGAs",IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems(pdf)
C45. D. Chen, J. Cong, F. Li and L. He,"Low Power Technology Mapping for FPGA Architectures with Dual Supply Voltages", the Twelfth International Symposium on Field Programmable Gate Arrays, Monterey, CA, pages: 109-117, February 2004(pdf)
C109.Yu Hu, Victor Shih, Rupak Majumdar and Lei He,
"Exploiting Symmetry in SAT-Based Boolean Matching for Heterogeneous
FPGA Technology Mapping", IEEE/ACM International Conf. on Computer-Aided
C110.Yu Hu, Satyaki
Das, Steve Trimberger and
Lei He, "Design, Synthesis and Evaluation of Heterogeneous FPGA with
Mixed LUTs and Macro-Gates", IEEE/ACM
International Conf. on Computer-Aided Design (ICCAD),
C116.Yu Hu, Victor Shih, Rupak Majumdar, and Lei He,
"FPGA Area Reduction by Multi-Output Function Based Sequential Resynthesis", IEEE/ACM Design Automation Conference,
C119. Yu Hu, Victor Shih, Rupak Majumdar, and Lei He, "FPGA Area Reduction by Multi-Output Function Based Sequential Resynthesis", IWLS 2008.(pdf)
C120. Yu Hu, Zhe Feng, Lei He, and Ruapk Majumdar, "Robust FPGA Resynthesis Based on Fault Tolerant Boolean Matching", accepted by ICCAD 2008. (Nominated for the Best Paper Award) (pdf)
C_SELSE. Ju-Yueh Lee, Yu Hu, Rupak Majumdar, Lei He, and Minming Li, Fault-Tolerant Resynthesis for Dual-Output LUTs, SELSE, 2009. (pdf)
P1. Yu Hu, Victor Shih, Rupak Majumdar, and Lei He, Mapping and Resynthesis for LUT-based FPGAs with an Efficient SAT-Based Boolean Matching, IWLS, 2008 (Best Contribution Award of the IEEE Programming Contest at IWLS 08).
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Last update: 01-31-2008.