| Reference for Verilog RTL
Synthesis
|
|
| Introduction to Logic Synthesis Using Verilog | |
| Book | |
| Verilog Tutorial | |
| Course slides from EE216A | |
| HDL Coding Styles Guide (from FPGA vendors' user manual) | |
NOTE: HDL parser, inference and optimization should follow the conventions defined in above papers. |
|
| An Academic RTL System | |
| Peter Jamieson, Jonathan Rose, A VERILOG RTL SYNTHESIS TOOL FOR HETEROGENEOUS FPGAS, FPL 2005. [pdf] [slides] [download source code] | |
| A Survey of Low Power RTL Synthesis | |
| M. Pedram and A. Abdollahi, Low-power RT-level synthesis techniques: a tutorial, IEE proceedings. Computers and digital techniques, 2005. [pdf] | |
| Xilinx FPGA documentations 8.1i | |
| Xilinx Development System Reference Guide (A comprehensive overview of Xilinx FPGA design flow and design style)[pdf] | |
| Xilinx Libraries Guide (Schematic and HDL template for primitives and macros present in (small) Xilinx FPGA family)[pdf] | |
| ISE 8.1i Quick Start Tutorial[pdf] | |
| Synthesis and Simulation Design Guide (Design and evaluation methodology, HDL coding styles and simulation flow)[pdf] | |
| Virtex-4 Libraries Guide for HDL Designs (HDL templates for Xilinx Virtex 4 primitives) [pdf] | |
| Virtex-4 Libraries Guide for Schematic Designs (Schematic templates for Xilinx Virtex 4 primitives and macros) [pdf] | |
| Reference of Xilinx DSP48 (from Synplify) | |
| Using Virtex4 DSP48 Components with the Synplify Pro Software [pdf] | |
| Synopsys Formality Documentations 2006.3 | |
| Formality Quick Reference [pdf] | |
| Formality User Guide[pdf] | |
| Formality Automated Setup File (SVF) [pdf] | |
| Layout-Driven Floorplanning for FPGAs | |
| Synopsys VCS Documentations 2006.6 | |
| Web documentation | |