oagFpga::VerilogDesign::Module Class Reference

A single Verilog module. More...

#include <oagFpgaVerilogDesign.h>

Collaboration diagram for oagFpga::VerilogDesign::Module:

[legend]List of all members.

Public Member Functions
	Module ()
	~Module ()
	Destructor.
Public Attributes
std::string	name
VerilogDesign *	design
std::list< Port * > *	ports
std::list< Declaration * >	declarations
std::list< Declaration * >	parameters
std::list< Declaration * > *	parameterOverrides
std::list< Assignment * > *	assignments
std::list< AlwaysBlock * > *	alwaysBlocks
std::list< Statement * > *	initialBlocks
std::list< Function * > *	functions
std::list< Instantiation * > *	instantiations

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Detailed Description

A single Verilog module.

This module may spawn several OpenAccess modules if multiple parameterizations exist.

Definition at line 55 of file oagFpgaVerilogDesign.h.

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Constructor & Destructor Documentation

oagFpga::VerilogDesign::Module::Module (   )  [inline]

Definition at line 70 of file oagFpgaVerilogDesign.h.

oagFpga::VerilogDesign::Module::~Module (   )

Destructor. Definition at line 27 of file oagFpgaVerilogDesign.cpp. References alwaysBlocks, assignments, declarations, functions, initialBlocks, parameterOverrides, parameters, and ports.

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Member Data Documentation

std::list<AlwaysBlock*>* oagFpga::VerilogDesign::Module::alwaysBlocks

Definition at line 65 of file oagFpgaVerilogDesign.h. Referenced by oagFpga::VerilogSynthesis::synthesizeModuleFunc(), and ~Module().

std::list<Assignment*>* oagFpga::VerilogDesign::Module::assignments

Definition at line 64 of file oagFpgaVerilogDesign.h. Referenced by oagFpga::VerilogSynthesis::synthesizeModuleAssigns(), and ~Module().

std::list<Declaration*> oagFpga::VerilogDesign::Module::declarations

Definition at line 61 of file oagFpgaVerilogDesign.h. Referenced by oagFpga::VerilogSynthesis::synthesizeModuleNets(), oagFpga::VerilogSynthesis::synthesizeModuleTerms(), and ~Module().

VerilogDesign* oagFpga::VerilogDesign::Module::design

Definition at line 59 of file oagFpgaVerilogDesign.h. Referenced by oagFpga::VerilogSynthesis::synthesizeModuleInsts().

std::list<Function*>* oagFpga::VerilogDesign::Module::functions

Definition at line 67 of file oagFpgaVerilogDesign.h. Referenced by ~Module().

std::list<Statement*>* oagFpga::VerilogDesign::Module::initialBlocks

Definition at line 66 of file oagFpgaVerilogDesign.h. Referenced by ~Module().

std::list<Instantiation*>* oagFpga::VerilogDesign::Module::instantiations

Definition at line 68 of file oagFpgaVerilogDesign.h. Referenced by oagFpga::VerilogSynthesis::synthesizeModuleInsts().

std::string oagFpga::VerilogDesign::Module::name

Definition at line 57 of file oagFpgaVerilogDesign.h. Referenced by oagFpga::VerilogSynthesis::getParameterizedModuleName(), oagFpga::VerilogSynthesis::synthesize(), oagFpga::VerilogSynthesis::synthesizeCase(), oagFpga::VerilogSynthesis::synthesizeCaseEasy(), oagFpga::VerilogSynthesis::synthesizeIf(), and oagFpga::VerilogSynthesis::synthesizeModule().

std::list<Declaration*>* oagFpga::VerilogDesign::Module::parameterOverrides

Definition at line 63 of file oagFpgaVerilogDesign.h. Referenced by ~Module().

std::list<Declaration*> oagFpga::VerilogDesign::Module::parameters

Definition at line 62 of file oagFpgaVerilogDesign.h. Referenced by oagFpga::VerilogSynthesis::getParameterizedModuleName(), oagFpga::VerilogSynthesis::synthesizeModule(), and ~Module().

std::list<Port*>* oagFpga::VerilogDesign::Module::ports

Definition at line 60 of file oagFpgaVerilogDesign.h. Referenced by oagFpga::VerilogSynthesis::synthesizeModuleTerms(), and ~Module().

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The documentation for this class was generated from the following files:

• oagFpgaVerilogDesign.h
• oagFpgaVerilogDesign.cpp

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