oagFpga.cpp File Reference

#include "oaDesignDB.h"
#include "oagFpga.h"
#include "oagFpgaManager.h"
#include "oagFpgaMapper.h"
#include "oagFpgaVerilogSynthesis.h"
#include "oagFpgaModuleCompiler.h"
#include <iostream>
#include "oagFpgaDebug.h"

Include dependency graph for oagFpga.cpp:

Go to the source code of this file.

Namespaces
namespace	oagFpga
namespace	std
Reading and writing functional descriptions from other formats
void	readVerilog (oa::oaLib *library, const char *filename)
	Reads a behavioral Verilog description into the netlist view.
void	readVerilog (oa::oaLib *library, const oa::oaScalarName &viewName, const char *filename)
	Reads a behavioral Verilog description.
void	YuTest (oa::oaLib *curLib, oa::oaView *curView, oa::oaModule *currentModule)
void	lutMap (oa::oaLib *curLib, oa::oaView *curView, oa::oaDesign *targetDesign, int lutSize=4, int cutsPerNode=200, bool flatten=false, char *clockNetName=NULL, char *clockTriggerName=NULL, char *resetNetName=NULL, char *resetTriggerName=NULL, char *objectiveName="area")
	Perform cut based technology mapping for LUT based FPGA.
Observer *	observer
	Safely casts an oaModNet* to an oaModBitNet*.
oa::oaLib *	YuTestCurLib
oa::oaView *	YuTestCurView
Functions
int	oagFpgaVerilog_yyparse ()
int	oagFpgaLib_yyparse ()
void	initialize ()
	Initializes Func package. Must be called before any use.
Variables
char *	oagFpgaVerilog_yyfilename
FILE *	oagFpgaVerilog_yyin
oagFpga::VerilogDesign *	oagFpgaVerilog_yydesign
FILE *	oagFpgaLib_yyin
oa::oaVarDataAppDef< oa::oaDesign > *	streamAppDef
	definitions for application extensions
oa::oaVoidPointerAppDef< oa::oaDesign > *	managerAppDef
oa::oaIntAppDef< oa::oaModBitNet > *	bbRefAppDef
oa::oaIntAppDef< oa::oaModBitNet > *	AiRefAppDef

---

Function Documentation

void oagFpga::initialize (   )

Initializes Func package. Must be called before any use. Initializes data structures for representing and manipulating functional information. The necessary AppDefs are created in the OpenAccess database. An Observer object is also created to intercept the file I/O operations on objects with functional representations. Definition at line 60 of file oagFpga.cpp. References oagFpga::AiRefAppDef, oagFpga::bbRefAppDef, oagFpga::managerAppDef, oagFpga::observer, and oagFpga::streamAppDef.

void oagFpga::lutMap (  oa::oaLib *  curLib, oa::oaView *  curView, oa::oaDesign *  targetDesign, int  lutSize = 4, int  cutsPerNode = 200, bool  flatten = false, char *  clockNetName = NULL, char *  clockTriggerName = NULL, char *  resetNetName = NULL, char *  resetTriggerName = NULL, char *  objectiveName = "area" )

Perform cut based technology mapping for LUT based FPGA. Parameters: library  library viewName  viewName targetDesign  The design which is gonna be mapped cutsPerNode  The number of cuts per node flatten  True if one needs to decompose the whole hierachy, false otherwise clockNet  The specified clock net, NULL if it's not specified clockTrigger  The specified clock trigger, NULL if it's not specified resetNet  The specified clock net, NULL if it's not specified resetTrigger  The specified clock trigger, NULL if it's not specified objective  Can be delay/area Definition at line 200 of file oagFpga.cpp. References oagFpga::MapperUtils::addGlobalClock(), oagFpga::MapperUtils::addGlobalReset(), oagFpga::MapperUtils::createLut(), oagFpga::MapperUtils::createSeq(), oagFpga::FpgaMapper::mapUtils, oagFpga::MapperUtils::printGateUsage(), oagFpga::MapperUtils::removeDanglingNets(), oagFpga::FpgaMapper::techmapArea(), oagFpga::FpgaMapper::techmapDelay(), oagFpga::YuTestCurLib, and oagFpga::YuTestCurView.

int oagFpgaLib_yyparse (   )

int oagFpgaVerilog_yyparse (   )

Referenced by oagFpga::readVerilog().

void oagFpga::readVerilog (  oa::oaLib *  library, const oa::oaScalarName &  viewName, const char *  filename )

Reads a behavioral Verilog description. Parameters: library  the library in which to find/create the cells described in the file view  the view in which to find/create the cells filename  the path of the Verilog file to read Definition at line 109 of file oagFpga.cpp. References oagFpgaVerilog_yydesign, oagFpgaVerilog_yyfilename, oagFpgaVerilog_yyin, and oagFpgaVerilog_yyparse(). Referenced by oagFpga::readVerilog().

void oagFpga::readVerilog (  oa::oaLib *  library, const char *  filename )

Reads a behavioral Verilog description into the netlist view. A view other than "netlist" can be specified with additional parameters. Parameters: library  the library in which to find/create the cells described in the file filename  the path of the Verilog file to read Definition at line 86 of file oagFpga.cpp. References oagFpga::readVerilog().

void oagFpga::YuTest (  oa::oaLib *  curLib, oa::oaView *  curView, oa::oaModule *  currentModule )

Definition at line 160 of file oagFpga.cpp.

---

Variable Documentation

oa::oaIntAppDef< oa::oaModBitNet > * oagFpga::AiRefAppDef

Definition at line 40 of file oagFpga.cpp. Referenced by oagFpga::ModuleCompiler::compileBBNode(), oagFpga::Manager::create(), oagFpga::Manager::destroy(), oagFpga::Manager::getNetToAiConnection(), oagFpga::initialize(), oagFpga::Manager::prepareNetToAiConnection(), oagFpga::Manager::removeNetToAiConnection(), and oagFpga::Manager::setNetToAiConnection().

oa::oaIntAppDef< oa::oaModBitNet > * oagFpga::bbRefAppDef

Definition at line 38 of file oagFpga.cpp. Referenced by oagFpga::Synthesis::assignMultiRef(), oagFpga::Synthesis::binaryBusInputOutputOpt(), oagFpga::Synthesis::binaryBusOpt(), oagFpga::Synthesis::binaryOpt(), oagFpga::Manager::create(), oagFpga::Synthesis::createModule(), oagFpga::Manager::destroy(), oagFpga::Manager::getNetToBBConnection(), oagFpga::initialize(), oagFpga::Synthesis::latch(), oagFpga::Synthesis::mux(), oagFpga::Synthesis::notOf(), oagFpga::Manager::prepareNetToBBConnection(), oagFpga::Synthesis::seq(), oagFpga::Manager::setNetToBBConnection(), oagFpga::Synthesis::unaryBusInputOutputOpt(), and oagFpga::Synthesis::unaryBusOpt().

oa::oaVoidPointerAppDef< oa::oaDesign > * oagFpga::managerAppDef

Definition at line 36 of file oagFpga.cpp. Referenced by oagFpga::ModuleCompiler::compileModules(), oagFpga::Manager::create(), oagFpga::Synthesis::createModule(), oagFpga::Manager::destroy(), oagFpga::Manager::get(), oagFpga::Manager::hasManager(), oagFpga::initialize(), and oagFpga::Manager::Manager().

FILE* oagFpgaLib_yyin

oagFpga::VerilogDesign* oagFpgaVerilog_yydesign

Referenced by oagFpga::readVerilog().

char* oagFpgaVerilog_yyfilename

Referenced by oagFpga::readVerilog().

FILE* oagFpgaVerilog_yyin

Referenced by oagFpga::readVerilog().

Observer * oagFpga::observer

Safely casts an oaModNet* to an oaModBitNet*. Definition at line 42 of file oagFpga.cpp. Referenced by oagFpga::initialize().

oa::oaVarDataAppDef< oa::oaDesign > * oagFpga::streamAppDef

definitions for application extensions Definition at line 34 of file oagFpga.cpp. Referenced by oagFpga::initialize(), oagFpga::Observer::onFirstOpen(), oagFpga::Observer::onPostSave(), and oagFpga::Observer::onPreSave().

oa::oaLib * oagFpga::YuTestCurLib

Definition at line 156 of file oagFpga.cpp. Referenced by oagFpga::lutMap().

oa::oaView * oagFpga::YuTestCurView

Definition at line 157 of file oagFpga.cpp. Referenced by oagFpga::lutMap().

---