oagFpgaVerilogParserYystype.h

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#if !defined(oagFpgaVerilogParserYystype_P)
#define oagFpgaVerilogParserYystype_P

#include "oagFpgaVerilogDesign.h"
#include <list>
#include <map>

using namespace oagFpga;

typedef union YYSTYPE {
    struct {
        bool                                negative;       // sign flag
        int                                 bits;           // bit length
        unsigned int                        value;          // integer value
        unsigned int                        zmask;          // mask of bits that were 'z'
        unsigned int                        xmask;          // mask of bits that were 'x'
    } number;
    char                                    *str;       // string

    VerilogDesign::Expression              *expression;
    std::list<VerilogDesign::Expression*>  *expressions;
    VerilogDesign::Primary                 *primary;
    std::list<VerilogDesign::Primary*>     *primaries;
    VerilogDesign::Bundle                  *bundle;
    
    VerilogDesign::Module                     *module;
    std::list<VerilogDesign::Port*>           *ports;
    std::list<VerilogDesign::PortConnection*> *portConnections;
    VerilogDesign::Assignment                 *assignment;
    VerilogDesign::Declaration                *declaration;
    VerilogDesign::PortConnection             *portConnection;
    VerilogDesign::Instantiation              *instantiation;
  
    VerilogDesign::Statement               *statement;
    std::list<VerilogDesign::Statement*>   *statements;
    std::list<VerilogDesign::Case*>        *cases;

    VerilogDesign::Trigger                 *trigger;
    std::list<VerilogDesign::Trigger*>     *triggers;
   
    struct {
        std::list<VerilogDesign::Assignment*>    *assignments;
        std::list<VerilogDesign::AlwaysBlock*>   *alwaysBlocks;
        std::list<VerilogDesign::Statement*>     *initialBlocks; 
        std::list<VerilogDesign::Instantiation*> *instantiations;
        std::list<VerilogDesign::Declaration*>   *declarations;        
        std::list<VerilogDesign::Function*>      *functions;
        std::list<VerilogDesign::Declaration*>   *parameterOverrides;
    } decls;
    
} YYSTYPE;

#define YYSTYPE_IS_DECLARED 1
#define YYSTYPE_IS_TRIVIAL 1

#endif

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