YYSTYPE Union Reference

#include <oagFpgaVerilogParserYystype.h>

Collaboration diagram for YYSTYPE:

[legend]List of all members.

Public Attributes
struct {
bool   negative
int   bits
unsigned int   value
unsigned int   zmask
unsigned int   xmask
}	number
char *	str
VerilogDesign::Expression *	expression
std::list< VerilogDesign::Expression * > *	expressions
VerilogDesign::Primary *	primary
std::list< VerilogDesign::Primary * > *	primaries
VerilogDesign::Bundle *	bundle
VerilogDesign::Module *	module
std::list< VerilogDesign::Port * > *	ports
std::list< VerilogDesign::PortConnection * > *	portConnections
VerilogDesign::Assignment *	assignment
VerilogDesign::Declaration *	declaration
VerilogDesign::PortConnection *	portConnection
VerilogDesign::Instantiation *	instantiation
VerilogDesign::Statement *	statement
std::list< VerilogDesign::Statement * > *	statements
std::list< VerilogDesign::Case * > *	cases
VerilogDesign::Trigger *	trigger
std::list< VerilogDesign::Trigger * > *	triggers
struct {
std::list< VerilogDesign::Assignment * > *   assignments
std::list< VerilogDesign::AlwaysBlock * > *   alwaysBlocks
std::list< VerilogDesign::Statement * > *   initialBlocks
std::list< VerilogDesign::Instantiation * > *   instantiations
std::list< VerilogDesign::Declaration * > *   declarations
std::list< VerilogDesign::Function * > *   functions
std::list< VerilogDesign::Declaration * > *   parameterOverrides
}	decls

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Member Data Documentation

std::list<VerilogDesign::AlwaysBlock*>* YYSTYPE::alwaysBlocks

Definition at line 44 of file oagFpgaVerilogParserYystype.h.

VerilogDesign::Assignment* YYSTYPE::assignment

Definition at line 30 of file oagFpgaVerilogParserYystype.h.

std::list<VerilogDesign::Assignment*>* YYSTYPE::assignments

Definition at line 43 of file oagFpgaVerilogParserYystype.h.

int YYSTYPE::bits

Definition at line 14 of file oagFpgaVerilogParserYystype.h.

VerilogDesign::Bundle* YYSTYPE::bundle

Definition at line 25 of file oagFpgaVerilogParserYystype.h.

std::list<VerilogDesign::Case*>* YYSTYPE::cases

Definition at line 37 of file oagFpgaVerilogParserYystype.h.

VerilogDesign::Declaration* YYSTYPE::declaration

Definition at line 31 of file oagFpgaVerilogParserYystype.h.

std::list<VerilogDesign::Declaration*>* YYSTYPE::declarations

Definition at line 47 of file oagFpgaVerilogParserYystype.h.

struct { ... } YYSTYPE::decls

VerilogDesign::Expression* YYSTYPE::expression

Definition at line 21 of file oagFpgaVerilogParserYystype.h.

std::list<VerilogDesign::Expression*>* YYSTYPE::expressions

Definition at line 22 of file oagFpgaVerilogParserYystype.h.

std::list<VerilogDesign::Function*>* YYSTYPE::functions

Definition at line 48 of file oagFpgaVerilogParserYystype.h.

std::list<VerilogDesign::Statement*>* YYSTYPE::initialBlocks

Definition at line 45 of file oagFpgaVerilogParserYystype.h.

VerilogDesign::Instantiation* YYSTYPE::instantiation

Definition at line 33 of file oagFpgaVerilogParserYystype.h.

std::list<VerilogDesign::Instantiation*>* YYSTYPE::instantiations

Definition at line 46 of file oagFpgaVerilogParserYystype.h.

VerilogDesign::Module* YYSTYPE::module

Definition at line 27 of file oagFpgaVerilogParserYystype.h.

bool YYSTYPE::negative

Definition at line 13 of file oagFpgaVerilogParserYystype.h.

struct { ... } YYSTYPE::number

std::list<VerilogDesign::Declaration*>* YYSTYPE::parameterOverrides

Definition at line 49 of file oagFpgaVerilogParserYystype.h.

VerilogDesign::PortConnection* YYSTYPE::portConnection

Definition at line 32 of file oagFpgaVerilogParserYystype.h.

std::list<VerilogDesign::PortConnection*>* YYSTYPE::portConnections

Definition at line 29 of file oagFpgaVerilogParserYystype.h.

std::list<VerilogDesign::Port*>* YYSTYPE::ports

Definition at line 28 of file oagFpgaVerilogParserYystype.h.

std::list<VerilogDesign::Primary*>* YYSTYPE::primaries

Definition at line 24 of file oagFpgaVerilogParserYystype.h.

VerilogDesign::Primary* YYSTYPE::primary

Definition at line 23 of file oagFpgaVerilogParserYystype.h.

VerilogDesign::Statement* YYSTYPE::statement

Definition at line 35 of file oagFpgaVerilogParserYystype.h.

std::list<VerilogDesign::Statement*>* YYSTYPE::statements

Definition at line 36 of file oagFpgaVerilogParserYystype.h.

char* YYSTYPE::str

Definition at line 19 of file oagFpgaVerilogParserYystype.h.

VerilogDesign::Trigger* YYSTYPE::trigger

Definition at line 39 of file oagFpgaVerilogParserYystype.h.

std::list<VerilogDesign::Trigger*>* YYSTYPE::triggers

Definition at line 40 of file oagFpgaVerilogParserYystype.h.

unsigned int YYSTYPE::value

Definition at line 15 of file oagFpgaVerilogParserYystype.h.

unsigned int YYSTYPE::xmask

Definition at line 17 of file oagFpgaVerilogParserYystype.h.

unsigned int YYSTYPE::zmask

Definition at line 16 of file oagFpgaVerilogParserYystype.h.

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The documentation for this union was generated from the following file:

• oagFpgaVerilogParserYystype.h

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