oagFpga::VerilogSynthesis Class Reference

Constructs OpenAccess objects and a functional description from a given VerilogDesign object. More...

#include <oagFpgaVerilogSynthesis.h>

Inheritance diagram for oagFpga::VerilogSynthesis:

[legend]Collaboration diagram for oagFpga::VerilogSynthesis:

[legend]List of all members.

Static Public Member Functions
void	synthesize (VerilogDesign *design)
	Synthesize a Verilog design into OpenAccess.
Protected Types
typedef map< string, ConstantValue >	ParameterValues
typedef list< LvalRef * >	LvalRefBus
enum	LvalType { LVAL_UNKNOWN, LVAL_UNCONDITIONAL, LVAL_CONDITIONAL, LVAL_FUNCTION }
Static Protected Member Functions
void	synthesizeModule (VerilogDesign::Module *module, list< ConstantValue > &parameters)
	Synthesize a Verilog module into an OpenAccess object.
void	synthesizeModuleNets ()
	Synthesize the nets in a Verilog module into OpenAccess objects.
void	synthesizeModuleTerms ()
	Synthesize the ports in a Verilog module into OpenAccess objects.
void	synthesizeModuleAssigns ()
	Synthesize the continuous assignments in a Verilog module.
void	synthesizeModuleInsts ()
	Synthesize the instantiations in a Verilog module into OpenAccess objects.
void	synthesizeModuleFunc ()
	Synthesize the behavioral descriptions in a Verilog module into a BB description.
void	synthesizeBehavioral (VerilogDesign::Statement *statement, ProceduralState &state, ParameterValues *parameters)
	Synthesize a behavioral statement.
void	synthesizeBlock (VerilogDesign::Statement *statement, ProceduralState &state, ParameterValues *parameters)
	Synthesize a block statement with local variable declaration and other statements.
void	synthesizeIf (VerilogDesign::Statement *statement, ProceduralState &state, ParameterValues *parameters)
	Synthesize a IF statement.
bool	synthesizeCaseEasy (VerilogDesign::Statement *statement, ProceduralState &state, ParameterValues *parameters)
	Synthesize a CASE statement where all branch conditions are constant, true will be returned if so, false otherwise. A big MUX is inferred.
void	synthesizeCase (VerilogDesign::Statement *statement, ProceduralState &state, ParameterValues *parameters)
	Synthesize a CASE statement.
void	synthesizeBlockingassignment (VerilogDesign::Statement *statement, ProceduralState &state, ParameterValues *parameters)
	Synthesize a behavioral statement.
void	synthesizeNonblockingassignment (VerilogDesign::Statement *statement, ProceduralState &state, ParameterValues *parameters)
	Synthesize a behavioral statement.
string	getParameterizedModuleName (VerilogDesign::Module *vModule, list< ConstantValue > &parameters)
	Creates a module name to reflect a set of parameters.
void	evaluateConstantExpression (ConstantValue &result, VerilogDesign::Expression *expression, ParameterValues *parameters)
	An error will be return if the expression is not constant.
bool	isConstantExpression (VerilogDesign::Expression *expression, ParameterValues *parameters)
	Tests if an expression is a constant or not.
bool	evaluateExpression (MultiRefBus &result, VerilogDesign::Expression *expression, ProceduralState *state, ParameterValues *parameters)
	Evaluate an expression.
void	evaluateLval (LvalRefBus &result, VerilogDesign::Expression *expression, ProceduralState *state, ParameterValues *parameters)
	Evaluate an lval.
MultiRef	getContextualValue (oa::oaModBitNet *net, ProceduralState *state)
	Return the MultiRef for a particular net, including any procedural assignment that it may have.
void	appendSuffix (string &root, const string suffix)
	Appends a suffix onto a string to construct a valid Verilog name.
bool	isAsynchronousSignal (oa::oaModBitNet *net, ProceduralState *state)
	Return true if a net is in the trigger list of the current state.
string	printBitNetName (oa::oaModBitNet *n)
Static Protected Attributes
Intermediate state
set< string >	finishedModules
VerilogDesign::Module *	currentVmodule
	The Verilog module currently being synthesized.
ParameterValues *	currentParams
	The parameters of the module currently being synthesized.
map< string, Bounds >	twoDimRegisters

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Detailed Description

Constructs OpenAccess objects and a functional description from a given VerilogDesign object.

All calls are static functions.

Definition at line 30 of file oagFpgaVerilogSynthesis.h.

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Member Typedef Documentation

typedef list<LvalRef*> oagFpga::VerilogSynthesis::LvalRefBus [protected]

Definition at line 140 of file oagFpgaVerilogSynthesis.h. Referenced by evaluateLval(), synthesizeBlockingassignment(), synthesizeModuleAssigns(), synthesizeModuleInsts(), and synthesizeNonblockingassignment().

typedef map<string, ConstantValue> oagFpga::VerilogSynthesis::ParameterValues [protected]

Definition at line 40 of file oagFpgaVerilogSynthesis.h. Referenced by getParameterizedModuleName(), and synthesizeModuleInsts().

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Member Enumeration Documentation

enum oagFpga::VerilogSynthesis::LvalType [protected]

Enumeration values: LVAL_UNKNOWN  LVAL_UNCONDITIONAL  LVAL_CONDITIONAL  LVAL_FUNCTION  Definition at line 115 of file oagFpgaVerilogSynthesis.h.

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Member Function Documentation

void oagFpga::VerilogSynthesis::appendSuffix (  string &  root, const string  suffix )  [static, protected]

Appends a suffix onto a string to construct a valid Verilog name. This routine is necessary because escaped Verilog names must end in a space. Parameters: root  the string on to which the suffix is appended suffix  Definition at line 4148 of file oagFpgaVerilogSynthesis.cpp. Referenced by evaluateExpression(), evaluateLval(), getParameterizedModuleName(), synthesizeBlock(), synthesizeModuleInsts(), and synthesizeModuleNets().

void oagFpga::VerilogSynthesis::evaluateConstantExpression (  ConstantValue &  result, VerilogDesign::Expression *  expression, ParameterValues *  parameters )  [static, protected]

An error will be return if the expression is not constant. Definition at line 2425 of file oagFpgaVerilogSynthesis.cpp. References oagFpga::VerilogDesign::Expression::bundle, DEBUG_PRINTLN, max, oagFpga::VerilogDesign::Expression::op1, oagFpga::VerilogDesign::Expression::op2, oagFpga::VerilogDesign::Expression::op3, oagFpga::VerilogDesign::Expression::primary, and oagFpga::VerilogDesign::Expression::type. Referenced by evaluateExpression(), evaluateLval(), getParameterizedModuleName(), synthesizeBlock(), synthesizeCase(), synthesizeCaseEasy(), synthesizeModule(), synthesizeModuleInsts(), and synthesizeModuleNets().

bool oagFpga::VerilogSynthesis::evaluateExpression (  MultiRefBus &  result, VerilogDesign::Expression *  expression, ProceduralState *  state, ParameterValues *  parameters )  [static, protected]

Evaluate an expression. Returns: True if there exist any asynchronous signals (the ones appear in the trigger list of a always block) in this expression. Definition at line 3059 of file oagFpgaVerilogSynthesis.cpp. References oagFpga::Synthesis::andOf(), appendSuffix(), oagFpga::Synthesis::arithmeticAdd(), oagFpga::Synthesis::arithmeticDivide(), oagFpga::Synthesis::arithmeticModulo(), oagFpga::Synthesis::arithmeticMultiply(), oagFpga::Synthesis::arithmeticSubtract(), oagFpga::VerilogDesign::Expression::bundle, oagFpga::Synthesis::createScalarNet(), currentVmodule, DEBUG_PRINTLN, oagFpga::Synthesis::equalTo(), evaluateConstantExpression(), oagFpga::Synthesis::findBusNet(), oagFpga::Synthesis::findBusNetBit(), oagFpga::Synthesis::findScalarNet(), getContextualValue(), oagFpga::Synthesis::greaterThan(), oagFpga::Synthesis::greaterThanEqual(), isAsynchronousSignal(), isConstantExpression(), oagFpga::VerilogSynthesis::ProceduralState::isFunction, oagFpga::Synthesis::lessThan(), oagFpga::Synthesis::lessThanEqual(), oagFpga::Synthesis::logicAnd(), oagFpga::Synthesis::logicNot(), oagFpga::Synthesis::logicOr(), oagFpga::Synthesis::multiBitConstant(), oagFpga::MultiRefBus, oagFpga::Synthesis::mux(), oagFpga::Synthesis::nandOf(), oagFpga::NEITHER, oagFpga::Synthesis::norOf(), oagFpga::Synthesis::notEqualTo(), oagFpga::Synthesis::notOf(), oagFpga::VerilogDesign::Expression::op1, oagFpga::VerilogDesign::Expression::op2, oagFpga::VerilogDesign::Expression::op3, oagFpga::Synthesis::orOf(), oagFpga::VerilogDesign::Expression::primary, oagFpga::Synthesis::reductionAnd(), oagFpga::Synthesis::reductionNand(), oagFpga::Synthesis::reductionNor(), oagFpga::Synthesis::reductionOr(), oagFpga::Synthesis::reductionXnor(), oagFpga::Synthesis::reductionXor(), twoDimRegisters, oagFpga::VerilogDesign::Expression::type, oagFpga::Synthesis::xnorOf(), oagFpga::Synthesis::xorOf(), and oagFpga::Synthesis::zeroExpand(). Referenced by synthesizeBlockingassignment(), synthesizeCase(), synthesizeCaseEasy(), synthesizeIf(), synthesizeModuleAssigns(), synthesizeModuleFunc(), synthesizeModuleInsts(), and synthesizeNonblockingassignment().

void oagFpga::VerilogSynthesis::evaluateLval (  LvalRefBus &  result, VerilogDesign::Expression *  expression, ProceduralState *  state, ParameterValues *  parameters )  [static, protected]

Evaluate an lval. Definition at line 2710 of file oagFpgaVerilogSynthesis.cpp. References appendSuffix(), oagFpga::VerilogDesign::Expression::bundle, oagFpga::Synthesis::createScalarNet(), DEBUG_PRINTLN, evaluateConstantExpression(), oagFpga::Synthesis::findBusNet(), oagFpga::Synthesis::findBusNetBit(), oagFpga::Synthesis::findScalarNet(), isConstantExpression(), oagFpga::VerilogSynthesis::ProceduralState::isFunction, LvalRefBus, oagFpga::MultiRefBus, oagFpga::VerilogDesign::Expression::primary, twoDimRegisters, and oagFpga::VerilogDesign::Expression::type. Referenced by synthesizeBlockingassignment(), synthesizeModuleAssigns(), synthesizeModuleInsts(), and synthesizeNonblockingassignment().

MultiRef oagFpga::VerilogSynthesis::getContextualValue (  oa::oaModBitNet *  net, ProceduralState *  state )  [static, protected]

Return the MultiRef for a particular net, including any procedural assignment that it may have. Definition at line 4125 of file oagFpgaVerilogSynthesis.cpp. References oagFpga::VerilogSynthesis::ProceduralState::blockingAssignments. Referenced by evaluateExpression().

string oagFpga::VerilogSynthesis::getParameterizedModuleName (  VerilogDesign::Module *  vModule, list< ConstantValue > &  parameters )  [static, protected]

Creates a module name to reflect a set of parameters. Returns a string to identify a version of a module with a particular set of parameters. Currently, the parameter values are appended to the module name and delimited with the "_" character. Definition at line 71 of file oagFpgaVerilogSynthesis.cpp. References appendSuffix(), evaluateConstantExpression(), oagFpga::VerilogDesign::Module::name, oagFpga::VerilogDesign::Module::parameters, and ParameterValues. Referenced by synthesizeModule(), and synthesizeModuleInsts().

bool oagFpga::VerilogSynthesis::isAsynchronousSignal (  oa::oaModBitNet *  net, ProceduralState *  state )  [static, protected]

Return true if a net is in the trigger list of the current state. Definition at line 3034 of file oagFpgaVerilogSynthesis.cpp. References oagFpga::VerilogSynthesis::ProceduralState::negTriggers, oagFpga::VerilogSynthesis::ProceduralState::nonClockTriggers, and oagFpga::VerilogSynthesis::ProceduralState::posTriggers. Referenced by evaluateExpression().

bool oagFpga::VerilogSynthesis::isConstantExpression (  VerilogDesign::Expression *  expression, ParameterValues *  parameters )  [static, protected]

Tests if an expression is a constant or not. This returns true only if all leaves of the expression are constants. Any expressions that involve nets or registers, regardless of whether the nets or regs are themselves constant will return false. Also, any expressions that involve redundancy and are functionally constant (i.e. x & !x) will not be identified and also return false. Definition at line 2641 of file oagFpgaVerilogSynthesis.cpp. References oagFpga::VerilogDesign::Expression::bundle, oagFpga::VerilogDesign::Expression::op1, oagFpga::VerilogDesign::Expression::op2, oagFpga::VerilogDesign::Expression::op3, oagFpga::VerilogDesign::Expression::primary, and oagFpga::VerilogDesign::Expression::type. Referenced by evaluateExpression(), evaluateLval(), synthesizeCase(), and synthesizeCaseEasy().

string oagFpga::VerilogSynthesis::printBitNetName (  oa::oaModBitNet *  n  )  [static, protected]

Definition at line 4222 of file oagFpgaVerilogSynthesis.cpp. Referenced by synthesizeModuleFunc().

void oagFpga::VerilogSynthesis::synthesize (  VerilogDesign *  vDesign  )  [static]

Synthesize a Verilog design into OpenAccess. Builds an OpenAccess module for every unparameterized Verilog module. Definition at line 39 of file oagFpgaVerilogSynthesis.cpp. References finishedModules, oagFpga::VerilogDesign::modules, oagFpga::VerilogDesign::Module::name, and synthesizeModule().

void oagFpga::VerilogSynthesis::synthesizeBehavioral (  VerilogDesign::Statement *  statement, ProceduralState &  state, ParameterValues *  parameters )  [static, protected]

Synthesize a behavioral statement. Definition at line 2368 of file oagFpgaVerilogSynthesis.cpp. References synthesizeBlock(), synthesizeBlockingassignment(), synthesizeCase(), synthesizeCaseEasy(), synthesizeIf(), synthesizeNonblockingassignment(), and oagFpga::VerilogDesign::Statement::type. Referenced by synthesizeBlock(), synthesizeCase(), synthesizeCaseEasy(), synthesizeIf(), and synthesizeModuleFunc().

void oagFpga::VerilogSynthesis::synthesizeBlock (  VerilogDesign::Statement *  statement, ProceduralState &  state, ParameterValues *  parameters )  [static, protected]

Synthesize a block statement with local variable declaration and other statements. Definition at line 1026 of file oagFpgaVerilogSynthesis.cpp. References appendSuffix(), oagFpga::VerilogDesign::Statement::begin_end, oagFpga::VerilogDesign::Statement::block, oagFpga::Synthesis::createBusNet(), oagFpga::Synthesis::createScalarNet(), DEBUG_PRINT, DEBUG_PRINTLN, DEBUG_PRINTMORE, oagFpga::VerilogDesign::Statement::declarations, evaluateConstantExpression(), oagFpga::Synthesis::findBusNet(), oagFpga::Synthesis::findScalarNet(), max, min, oagFpga::VerilogDesign::Declaration::name, oagFpga::VerilogDesign::Declaration::start, oagFpga::VerilogDesign::Declaration::start2D, oagFpga::VerilogDesign::Declaration::stop, oagFpga::VerilogDesign::Declaration::stop2D, synthesizeBehavioral(), twoDimRegisters, and oagFpga::VerilogDesign::Declaration::type. Referenced by synthesizeBehavioral().

void oagFpga::VerilogSynthesis::synthesizeBlockingassignment (  VerilogDesign::Statement *  statement, ProceduralState &  state, ParameterValues *  parameters )  [static, protected]

Synthesize a behavioral statement. Definition at line 2178 of file oagFpgaVerilogSynthesis.cpp. References oagFpga::VerilogDesign::Statement::assign, oagFpga::VerilogSynthesis::ProceduralState::blockingAssignments, oagFpga::Synthesis::constantZero(), DEBUG_PRINTLN, evaluateExpression(), evaluateLval(), oagFpga::VerilogSynthesis::ProceduralState::functionAssignments, oagFpga::VerilogSynthesis::ProceduralState::isFunction, oagFpga::VerilogDesign::Statement::lval, LvalRefBus, oagFpga::MultiRefBus, and oagFpga::VerilogDesign::Statement::rval. Referenced by synthesizeBehavioral().

void oagFpga::VerilogSynthesis::synthesizeCase (  VerilogDesign::Statement *  statement, ProceduralState &  state, ParameterValues *  parameters )  [static, protected]

Synthesize a CASE statement. Definition at line 1877 of file oagFpgaVerilogSynthesis.cpp. References oagFpga::VerilogDesign::Case::action, oagFpga::Synthesis::andOf(), oagFpga::VerilogSynthesis::ProceduralState::blockingAssignments, oagFpga::VerilogDesign::Statement::cases, oagFpga::VerilogDesign::Statement::condition, oagFpga::VerilogDesign::Case::conditions, oagFpga::Synthesis::constantOne(), oagFpga::Synthesis::constantZero(), currentVmodule, DEBUG_PRINTLN, oagFpga::Synthesis::equalTo(), evaluateConstantExpression(), evaluateExpression(), oagFpga::VerilogDesign::Statement::ifc, isConstantExpression(), oagFpga::VerilogDesign::Case::isDefault, oagFpga::Synthesis::latch(), oagFpga::MultiRefBus, oagFpga::VerilogDesign::Module::name, oagFpga::VerilogSynthesis::ProceduralState::nonblockingAssignments, oagFpga::Synthesis::notOf(), oagFpga::Synthesis::orOf(), oagFpga::Synthesis::reductionOr(), synthesizeBehavioral(), oagFpga::VerilogDesign::Statement::type, and oagFpga::Synthesis::zeroExpand(). Referenced by synthesizeBehavioral().

bool oagFpga::VerilogSynthesis::synthesizeCaseEasy (  VerilogDesign::Statement *  statement, ProceduralState &  state, ParameterValues *  parameters )  [static, protected]

Synthesize a CASE statement where all branch conditions are constant, true will be returned if so, false otherwise. A big MUX is inferred. Definition at line 1378 of file oagFpgaVerilogSynthesis.cpp. References oagFpga::VerilogDesign::Case::action, oagFpga::VerilogSynthesis::ProceduralState::blockingAssignments, oagFpga::VerilogDesign::Statement::cases, oagFpga::VerilogDesign::Statement::condition, oagFpga::VerilogDesign::Case::conditions, oagFpga::Synthesis::constantOne(), oagFpga::Synthesis::constantZero(), currentVmodule, DEBUG_PRINTLN, evaluateConstantExpression(), evaluateExpression(), oagFpga::VerilogDesign::Statement::ifc, isConstantExpression(), oagFpga::VerilogDesign::Case::isDefault, oagFpga::Synthesis::latch(), oagFpga::MultiRefBus, oagFpga::Synthesis::mux(), oagFpga::VerilogDesign::Module::name, oagFpga::VerilogSynthesis::ProceduralState::nonblockingAssignments, synthesizeBehavioral(), oagFpga::VerilogDesign::Statement::type, and oagFpga::Synthesis::zeroExpand(). Referenced by synthesizeBehavioral().

void oagFpga::VerilogSynthesis::synthesizeIf (  VerilogDesign::Statement *  statement, ProceduralState &  state, ParameterValues *  parameters )  [static, protected]

Synthesize a IF statement. Definition at line 1135 of file oagFpgaVerilogSynthesis.cpp. References oagFpga::VerilogSynthesis::ProceduralState::aData, oagFpga::VerilogSynthesis::ProceduralState::aLoad, oagFpga::VerilogSynthesis::ProceduralState::blockingAssignments, oagFpga::VerilogDesign::Statement::condition, currentVmodule, oagFpga::VerilogSynthesis::ProceduralState::curTrigger, DEBUG_PRINTLN, evaluateExpression(), oagFpga::VerilogDesign::Statement::ifc, oagFpga::VerilogDesign::Statement::ifFalse, oagFpga::VerilogDesign::Statement::ifTrue, oagFpga::VerilogSynthesis::ProceduralState::isRegister, oagFpga::Synthesis::latch(), oagFpga::MultiRefBus, oagFpga::Synthesis::mux(), oagFpga::VerilogDesign::Module::name, oagFpga::NEITHER, oagFpga::VerilogSynthesis::ProceduralState::nonblockingAssignments, oagFpga::Synthesis::notOf(), oagFpga::VerilogSynthesis::ProceduralState::pStateType, oagFpga::Synthesis::reductionOr(), synthesizeBehavioral(), and oagFpga::MultiRef::type. Referenced by synthesizeBehavioral().

void oagFpga::VerilogSynthesis::synthesizeModule (  VerilogDesign::Module *  vModule, list< ConstantValue > &  parameters )  [static, protected]

Synthesize a Verilog module into an OpenAccess object. Builds an OpenAccess module for a Verilog module and a set of parameters. Because the parameters can significantly affect the structure of netlist, parameterization must be done at this point. The different versions of the same module with differing parameters will be identified by name. Definition at line 145 of file oagFpgaVerilogSynthesis.cpp. References oagFpga::Synthesis::createModule(), currentParams, currentVmodule, DEBUG_PRINTLN, evaluateConstantExpression(), finishedModules, getParameterizedModuleName(), oagFpga::VerilogDesign::Module::name, oagFpga::VerilogDesign::Module::parameters, oagFpga::Manager::print(), synthesizeModuleAssigns(), synthesizeModuleFunc(), synthesizeModuleInsts(), synthesizeModuleNets(), and synthesizeModuleTerms(). Referenced by synthesize(), and synthesizeModuleInsts().

void oagFpga::VerilogSynthesis::synthesizeModuleAssigns (   )  [static, protected]

Synthesize the continuous assignments in a Verilog module. One of several things is done with a continuous assignment. If the assignment involves a constant or two nets, the objects are marked as equivalent nets in OpenAccess. If the assignment involves any sort of functional operator, the assign will be implemented through the attached BB graph. Definition at line 444 of file oagFpgaVerilogSynthesis.cpp. References oagFpga::VerilogDesign::Module::assignments, oagFpga::Synthesis::assignMultiRef(), oagFpga::Synthesis::constantZero(), currentParams, currentVmodule, DEBUG_PRINTLN, evaluateExpression(), evaluateLval(), oagFpga::VerilogDesign::Assignment::lval, LvalRefBus, oagFpga::MultiRefBus, and oagFpga::VerilogDesign::Assignment::value. Referenced by synthesizeModule().

void oagFpga::VerilogSynthesis::synthesizeModuleFunc (   )  [static, protected]

Synthesize the behavioral descriptions in a Verilog module into a BB description. Builds the associated BB graph to describe the Verilog behavior description. Definition at line 777 of file oagFpgaVerilogSynthesis.cpp. References oagFpga::VerilogDesign::AlwaysBlock::action, oagFpga::VerilogSynthesis::ProceduralState::aData, oagFpga::VerilogSynthesis::ProceduralState::aLoad, oagFpga::VerilogDesign::Module::alwaysBlocks, oagFpga::Synthesis::assignMultiRef(), oagFpga::MultiRef::bb, oagFpga::VerilogSynthesis::ProceduralState::blockingAssignments, currentParams, currentVmodule, DEBUG_PRINTLN, evaluateExpression(), oagFpga::VerilogSynthesis::ProceduralState::isRegister, oagFpga::MultiRefBus, oagFpga::VerilogSynthesis::ProceduralState::negTriggers, oagFpga::NET, oagFpga::VerilogDesign::Trigger::net, oagFpga::VerilogSynthesis::ProceduralState::nonblockingAssignments, oagFpga::VerilogSynthesis::ProceduralState::nonClockTriggers, oagFpga::VerilogSynthesis::ProceduralState::normalTriggers, oagFpga::VerilogSynthesis::ProceduralState::posTriggers, printBitNetName(), oagFpga::Synthesis::seq(), synthesizeBehavioral(), oagFpga::VerilogDesign::AlwaysBlock::triggers, and oagFpga::VerilogDesign::Trigger::type. Referenced by synthesizeModule().

void oagFpga::VerilogSynthesis::synthesizeModuleInsts (   )  [static, protected]

Synthesize the instantiations in a Verilog module into OpenAccess objects. Builds OpenAccess insts for a Verilog structural instantiations. Definition at line 494 of file oagFpgaVerilogSynthesis.cpp. References appendSuffix(), oagFpga::Synthesis::assignMultiRef(), oagFpga::VerilogDesign::Instantiation::connections, oagFpga::Synthesis::connectPort(), oagFpga::Synthesis::createBusNet(), oagFpga::Synthesis::createScalarNet(), currentParams, currentVmodule, DEBUG_PRINTLN, oagFpga::VerilogDesign::Module::design, evaluateConstantExpression(), evaluateExpression(), evaluateLval(), oagFpga::Synthesis::findModule(), getParameterizedModuleName(), oagFpga::Synthesis::instantiateModule(), oagFpga::VerilogDesign::Module::instantiations, LvalRefBus, oagFpga::VerilogDesign::modules, oagFpga::MultiRefBus, oagFpga::VerilogDesign::PortConnection::name, oagFpga::VerilogDesign::Instantiation::name, oagFpga::MultiRef::net, oagFpga::Synthesis::notOf(), oagFpga::VerilogDesign::Instantiation::parameters, ParameterValues, oagFpga::VerilogDesign::PortConnection::position, oagFpga::VerilogDesign::Instantiation::primitive, QUIT_ON_INTERNAL_ERROR, oagFpga::Synthesis::reductionAnd(), oagFpga::Synthesis::reductionNand(), oagFpga::Synthesis::reductionNor(), oagFpga::Synthesis::reductionOr(), oagFpga::Synthesis::reductionXnor(), oagFpga::Synthesis::reductionXor(), synthesizeModule(), oagFpga::MultiRef::type, oagFpga::VerilogDesign::Instantiation::type, and oagFpga::VerilogDesign::PortConnection::value. Referenced by synthesizeModule().

void oagFpga::VerilogSynthesis::synthesizeModuleNets (   )  [static, protected]

Synthesize the nets in a Verilog module into OpenAccess objects. Builds OpenAccess nets for a Verilog wires, integers, and regs. Definition at line 224 of file oagFpgaVerilogSynthesis.cpp. References appendSuffix(), oagFpga::Synthesis::createBusNet(), oagFpga::Synthesis::createScalarNet(), currentParams, currentVmodule, DEBUG_PRINT, DEBUG_PRINTLN, DEBUG_PRINTMORE, oagFpga::VerilogDesign::Module::declarations, evaluateConstantExpression(), oagFpga::Synthesis::findBusNet(), oagFpga::Synthesis::findScalarNet(), max, min, oagFpga::VerilogDesign::Declaration::name, oagFpga::VerilogDesign::Declaration::start, oagFpga::VerilogDesign::Declaration::start2D, oagFpga::VerilogDesign::Declaration::stop, oagFpga::VerilogDesign::Declaration::stop2D, twoDimRegisters, and oagFpga::VerilogDesign::Declaration::type. Referenced by synthesizeModule().

void oagFpga::VerilogSynthesis::synthesizeModuleTerms (   )  [static, protected]

Synthesize the ports in a Verilog module into OpenAccess objects. Builds OpenAccess terms for a Verilog ports. Definition at line 379 of file oagFpgaVerilogSynthesis.cpp. References oagFpga::Synthesis::createTerm(), currentVmodule, DEBUG_PRINTLN, oagFpga::VerilogDesign::Module::declarations, oagFpga::VerilogDesign::Port::externalName, oagFpga::Synthesis::findNet(), oagFpga::VerilogDesign::Port::internalName, oagFpga::VerilogDesign::Declaration::name, oagFpga::VerilogDesign::Module::ports, and oagFpga::VerilogDesign::Declaration::type. Referenced by synthesizeModule().

void oagFpga::VerilogSynthesis::synthesizeNonblockingassignment (  VerilogDesign::Statement *  statement, ProceduralState &  state, ParameterValues *  parameters )  [static, protected]

Synthesize a behavioral statement. Definition at line 2277 of file oagFpgaVerilogSynthesis.cpp. References oagFpga::VerilogDesign::Statement::assign, oagFpga::Synthesis::constantZero(), DEBUG_PRINTLN, evaluateExpression(), evaluateLval(), oagFpga::VerilogDesign::Statement::lval, LvalRefBus, oagFpga::MultiRefBus, oagFpga::VerilogSynthesis::ProceduralState::nonblockingAssignments, and oagFpga::VerilogDesign::Statement::rval. Referenced by synthesizeBehavioral().

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Member Data Documentation

VerilogSynthesis::ParameterValues * oagFpga::VerilogSynthesis::currentParams [static, protected]

The parameters of the module currently being synthesized. Definition at line 24 of file oagFpgaVerilogSynthesis.cpp. Referenced by synthesizeModule(), synthesizeModuleAssigns(), synthesizeModuleFunc(), synthesizeModuleInsts(), and synthesizeModuleNets().

VerilogDesign::Module * oagFpga::VerilogSynthesis::currentVmodule [static, protected]

The Verilog module currently being synthesized. Definition at line 23 of file oagFpgaVerilogSynthesis.cpp. Referenced by evaluateExpression(), synthesizeCase(), synthesizeCaseEasy(), synthesizeIf(), synthesizeModule(), synthesizeModuleAssigns(), synthesizeModuleFunc(), synthesizeModuleInsts(), synthesizeModuleNets(), and synthesizeModuleTerms().

set< string > oagFpga::VerilogSynthesis::finishedModules [static, protected]

Definition at line 25 of file oagFpgaVerilogSynthesis.cpp. Referenced by synthesize(), and synthesizeModule().

map< string, VerilogSynthesis::Bounds > oagFpga::VerilogSynthesis::twoDimRegisters [static, protected]

Definition at line 26 of file oagFpgaVerilogSynthesis.cpp. Referenced by evaluateExpression(), evaluateLval(), synthesizeBlock(), and synthesizeModuleNets().

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The documentation for this class was generated from the following files:

• oagFpgaVerilogSynthesis.h
• oagFpgaVerilogSynthesis.cpp

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