- a -

• ADD : oagFpga::VerilogDesign::Expression, oagFpga::RtlNode
• AND : oagFpga::VerilogDesign::Instantiation

- b -

• BITWISE_AND : oagFpga::VerilogDesign::Expression, oagFpga::RtlNode
• BITWISE_NAND : oagFpga::VerilogDesign::Expression, oagFpga::RtlNode
• BITWISE_NOR : oagFpga::VerilogDesign::Expression, oagFpga::RtlNode
• BITWISE_NOT : oagFpga::VerilogDesign::Expression, oagFpga::RtlNode
• BITWISE_OR : oagFpga::VerilogDesign::Expression, oagFpga::RtlNode
• BITWISE_XNOR : oagFpga::VerilogDesign::Expression, oagFpga::RtlNode
• BITWISE_XOR : oagFpga::VerilogDesign::Expression, oagFpga::RtlNode
• BLOCK : oagFpga::VerilogDesign::Statement
• BLOCKING_ASSIGNMENT : oagFpga::VerilogDesign::Statement
• BOTH : oagFpga::VerilogDesign::Trigger
• BUF : oagFpga::VerilogDesign::Instantiation
• BUNDLE : oagFpga::VerilogDesign::Expression, oagFpga::RtlNode

- c -

• CASE : oagFpga::VerilogDesign::Statement
• CASEX : oagFpga::VerilogDesign::Statement
• CASEZ : oagFpga::VerilogDesign::Statement
• CONST : oagFpga::VerilogDesign::Primary
• CONSTANT0 : oagFpga::RtlNode
• CONSTANT1 : oagFpga::RtlNode
• CONTROL : oagFpga::RtlNode

- d -

• DFF : oagFpga::RtlNode
• DIVIDE : oagFpga::VerilogDesign::Expression, oagFpga::RtlNode

- e -

• EQUAL : oagFpga::VerilogDesign::Expression, oagFpga::RtlNode

- f -

• FUNCTION_CALL : oagFpga::VerilogDesign::Primary

- g -

• GREATER_THAN : oagFpga::VerilogDesign::Expression, oagFpga::RtlNode
• GREATER_THAN_EQUAL : oagFpga::VerilogDesign::Expression, oagFpga::RtlNode

- i -

• IF : oagFpga::VerilogDesign::Statement
• IF_ELSE : oagFpga::VerilogDesign::Expression, oagFpga::RtlNode
• INOUT : oagFpga::VerilogDesign::Declaration
• INPUT : oagFpga::VerilogDesign::Declaration
• ISNT_PRIMITIVE : oagFpga::VerilogDesign::Instantiation

- l -

• LATCH : oagFpga::RtlNode
• LEFT_SHIFT : oagFpga::VerilogDesign::Expression, oagFpga::RtlNode
• LESS_THAN : oagFpga::VerilogDesign::Expression, oagFpga::RtlNode
• LESS_THAN_EQUAL : oagFpga::VerilogDesign::Expression, oagFpga::RtlNode
• LOGICAL_AND : oagFpga::VerilogDesign::Expression, oagFpga::RtlNode
• LOGICAL_NOT : oagFpga::VerilogDesign::Expression, oagFpga::RtlNode
• LOGICAL_OR : oagFpga::VerilogDesign::Expression, oagFpga::RtlNode
• LVAL_CONDITIONAL : oagFpga::VerilogSynthesis
• LVAL_FUNCTION : oagFpga::VerilogSynthesis
• LVAL_UNCONDITIONAL : oagFpga::VerilogSynthesis
• LVAL_UNKNOWN : oagFpga::VerilogSynthesis

- m -

• MODULO : oagFpga::VerilogDesign::Expression, oagFpga::RtlNode
• MULTIPLY : oagFpga::VerilogDesign::Expression, oagFpga::RtlNode

- n -

• NAND : oagFpga::VerilogDesign::Instantiation
• NEGATE : oagFpga::VerilogDesign::Expression, oagFpga::RtlNode
• NEGEDGE : oagFpga::VerilogDesign::Trigger, oagFpga::MapperUtils, oagFpga::FpgaMapper
• NET : oagFpga::VerilogDesign::Primary
• NONBLOCKING_ASSIGNMENT : oagFpga::VerilogDesign::Statement
• NOP : oagFpga::VerilogDesign::Statement
• NOR : oagFpga::VerilogDesign::Instantiation
• NOT : oagFpga::VerilogDesign::Instantiation
• NOTEQUAL : oagFpga::VerilogDesign::Expression, oagFpga::RtlNode
• NULL_FUNC : oagFpga::RtlNode

- o -

• OPERATOR : oagFpga::RtlNode
• OR : oagFpga::VerilogDesign::Instantiation
• OUTPUT : oagFpga::VerilogDesign::Declaration

- p -

• PARAMETER : oagFpga::VerilogDesign::Declaration
• POSEDGE : oagFpga::VerilogDesign::Trigger, oagFpga::MapperUtils, oagFpga::FpgaMapper
• PRIMARY : oagFpga::VerilogDesign::Expression, oagFpga::RtlNode
• PSTATE_ASYNC : oagFpga::VerilogSynthesis::ProceduralState
• PSTATE_SYNC : oagFpga::VerilogSynthesis::ProceduralState

- r -

• REDUCTION_AND : oagFpga::VerilogDesign::Expression, oagFpga::RtlNode
• REDUCTION_NAND : oagFpga::VerilogDesign::Expression, oagFpga::RtlNode
• REDUCTION_NOR : oagFpga::VerilogDesign::Expression, oagFpga::RtlNode
• REDUCTION_OR : oagFpga::VerilogDesign::Expression, oagFpga::RtlNode
• REDUCTION_XNOR : oagFpga::VerilogDesign::Expression, oagFpga::RtlNode
• REDUCTION_XOR : oagFpga::VerilogDesign::Expression, oagFpga::RtlNode
• REG : oagFpga::VerilogDesign::Declaration
• RIGHT_SHIFT : oagFpga::VerilogDesign::Expression, oagFpga::RtlNode

- s -

• SEQ : oagFpga::RtlNode
• SUBTRACT : oagFpga::VerilogDesign::Expression, oagFpga::RtlNode
• SUPPLY0 : oagFpga::VerilogDesign::Declaration
• SUPPLY1 : oagFpga::VerilogDesign::Declaration

- t -

• TERMINAL : oagFpga::RtlNode
• TRI : oagFpga::VerilogDesign::Declaration
• TRI0 : oagFpga::VerilogDesign::Declaration
• TRI1 : oagFpga::VerilogDesign::Declaration
• TRIAND : oagFpga::VerilogDesign::Declaration
• TRIOR : oagFpga::VerilogDesign::Declaration

- u -

• UNKNOWN : oagFpga::VerilogDesign::Primary, oagFpga::VerilogDesign::Expression, oagFpga::VerilogDesign::Trigger, oagFpga::VerilogDesign::Declaration, oagFpga::RtlNode

- w -

• WIRE : oagFpga::VerilogDesign::Declaration
• WIREAND : oagFpga::VerilogDesign::Declaration
• WIREOR : oagFpga::VerilogDesign::Declaration

- x -

• XNOR : oagFpga::VerilogDesign::Instantiation
• XOR : oagFpga::VerilogDesign::Instantiation

---