OA Gear Fpga: Class Members - Functions

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- a -

addConditional() : oagFpga::VerilogSynthesis::LvalRef
addGlobalClock() : oagFpga::MapperUtils
addGlobalReset() : oagFpga::MapperUtils
addLeafLibrary() : oagFpga::Synthesis
addLeafView() : oagFpga::Synthesis
addNode() : oagFpga::RtlGraph
addTrivialGates() : oagFpga::FpgaMapper
AiModRef() : oagFpga::AiModRef
AlwaysBlock() : oagFpga::VerilogDesign::AlwaysBlock
andOf() : oagFpga::Synthesis, oagFpga::ModuleCompiler, oagFpga::AiModGraph
annotateAsynchronousSignal() : oagFpga::ModuleCompiler
appendSuffix() : oagFpga::VerilogSynthesis
arithmeticAdd() : oagFpga::Synthesis, oagFpga::ModuleCompiler
arithmeticDivide() : oagFpga::Synthesis, oagFpga::ModuleCompiler
arithmeticModulo() : oagFpga::Synthesis, oagFpga::ModuleCompiler
arithmeticMultiply() : oagFpga::Synthesis, oagFpga::ModuleCompiler
arithmeticSubtract() : oagFpga::Synthesis, oagFpga::ModuleCompiler
Assignment() : oagFpga::VerilogDesign::Assignment
assignMultiRef() : oagFpga::Synthesis

- b -

BBRef2AiRef() : oagFpga::ModuleCompiler
binaryBusInputOutputOpt() : oagFpga::Synthesis, oagFpga::RtlGraph
binaryBusOpt() : oagFpga::Synthesis, oagFpga::RtlGraph
binaryOpt() : oagFpga::Synthesis, oagFpga::RtlGraph
bitMux() : oagFpga::RtlGraph
bitSeq() : oagFpga::RtlGraph
buildNetlist() : oagFpga::RtlGraph
Bundle() : oagFpga::VerilogDesign::Bundle
busMux() : oagFpga::RtlGraph
busNet2Ai() : oagFpga::ModuleCompiler

- c -

Case() : oagFpga::VerilogDesign::Case
checkForExistenceOfDesign() : oagFpga::Synthesis
chooseEquivalent() : oagFpga::AiModGraph
clear() : oagFunc::SimOcc, oagFpga::SimMod
clearExternalReferences() : oagFpga::AiModGraph
clearKfeasibleCuts() : oagFpga::AiModGraph
compileBBNode() : oagFpga::ModuleCompiler
compileFunctionalBBNode() : oagFpga::ModuleCompiler
compileFunctionalMuxBBNode() : oagFpga::ModuleCompiler
compileFunctionalOptBBNode() : oagFpga::ModuleCompiler
compileFunctionalSeqBBNode() : oagFpga::ModuleCompiler
compileModules() : oagFpga::ModuleCompiler
compileOneModule() : oagFpga::ModuleCompiler
ConditionalLvalRef() : oagFpga::VerilogSynthesis::ConditionalLvalRef
connectEquivalentNetsInGraph() : oagFpga::ModGraph, oagFpga::AiModGraph
connectPort() : oagFpga::Synthesis
constantOne() : oagFpga::Synthesis, oagFpga::RtlGraph, oagFpga::OccGraph, oagFpga::ModGraph, oagFpga::AiModGraph
constantZero() : oagFpga::Synthesis, oagFpga::RtlGraph, oagFpga::OccGraph, oagFpga::ModGraph, oagFpga::AiModGraph
convertAiModRefListToRefList() : oagFpga::AiModGraph
convertModRefListToRefList() : oagFpga::ModGraph
convertRefListToAiModRefList() : oagFpga::AiModGraph
convertRefListToModRefList() : oagFpga::ModGraph
convertRefVectorToAiModRefVector() : oagFpga::AiModGraph
convertRefVectorToModRefVector() : oagFpga::ModGraph
create() : oagFpga::Manager
createBusNet() : oagFpga::Synthesis
createLut() : oagFpga::MapperUtils
createModule() : oagFpga::Synthesis
createScalarNet() : oagFpga::Synthesis
createSeq() : oagFpga::MapperUtils
createTerm() : oagFpga::Synthesis

- d -

Declaration() : oagFpga::VerilogDesign::Declaration
decrementExternalReferences() : oagFpga::AiModGraph
destroy() : oagFpga::Manager
detach() : oagFpga::AiModGraph

- e -

enumerateKfeasibleCuts() : oagFpga::AiModGraph
equalTo() : oagFpga::Synthesis, oagFpga::ModuleCompiler
evaluateConstantExpression() : oagFpga::VerilogSynthesis
evaluateExpression() : oagFpga::VerilogSynthesis
evaluateLval() : oagFpga::VerilogSynthesis
Expression() : oagFpga::VerilogDesign::Expression

- f -

failIfInDifferentModules() : oagFpga::ModGraph, oagFpga::AiModGraph
findBusNet() : oagFpga::Synthesis
findBusNetBit() : oagFpga::Synthesis
findDriverOfEquivalentNets() : oagFpga::ModGraph, oagFpga::AiModGraph
findModule() : oagFpga::Synthesis
findNet() : oagFpga::Synthesis
findScalarNet() : oagFpga::Synthesis
FpgaMapper() : oagFpga::FpgaMapper, oagFpga::MapperUtils
fullAdder() : oagFpga::ModuleCompiler
Function() : oagFpga::VerilogDesign::Function
FunctionVariableAssignment() : oagFpga::VerilogSynthesis::FunctionVariableAssignment

- g -

generateRandomInputVectors() : oagFunc::SimOcc, oagFpga::SimMod
generateRandomStateVectors() : oagFunc::SimOcc, oagFpga::SimMod
get() : oagFpga::Manager
getAiGraph() : oagFpga::Manager
getAllConnections() : oagFpga::OccGraph, oagFpga::AiModGraph
getAllNodes() : oagFpga::AiModGraph
getAndLeft() : oagFpga::AiModGraph
getAndRight() : oagFpga::AiModGraph
getBBNodeNum() : oagFpga::RtlGraph
getConstants() : oagFpga::OccGraph
getContextualValue() : oagFpga::VerilogSynthesis
getCumulativeAreaCost() : oagFpga::FpgaMapper
getCumulativeDelayCost() : oagFpga::FpgaMapper
getEquivalents() : oagFpga::AiModGraph
getExternalTerminalConnection() : oagFpga::RtlGraph
getFanin() : oagFpga::RtlGraph, oagFpga::ModGraph
getFaninCone() : oagFpga::AiModGraph
getFaninRoots() : oagFpga::AiModGraph
getFanout() : oagFpga::RtlGraph, oagFpga::OccGraph, oagFpga::ModGraph, oagFpga::AiModGraph
getFanoutCone() : oagFpga::AiModGraph
getFanoutOfEquivalentNodes() : oagFpga::AiModGraph
getFanoutRoots() : oagFpga::AiModGraph
getGraph() : oagFpga::ModGraph, oagFpga::AiModGraph
getInputs() : oagFpga::OccGraph, oagFpga::AiModGraph
getLocalStates() : oagFpga::OccGraph, oagFpga::AiModGraph
getLut() : oagFpga::MapperUtils
getModRef() : oagFpga::OccRef
getNetToAiConnection() : oagFpga::Manager, oagFpga::AiModGraph
getNetToBBAllEquivConnections() : oagFpga::OccGraph
getNetToBBConnection() : oagFpga::OccGraph, oagFpga::ModGraph, oagFpga::Manager
getNextState() : oagFpga::RtlGraph, oagFpga::OccGraph, oagFpga::ModGraph, oagFpga::AiModGraph
getNode() : oagFpga::RtlGraph
getNodeOptType() : oagFpga::RtlGraph, oagFpga::ModGraph
getNodeSeqType() : oagFpga::RtlGraph, oagFpga::ModGraph
getNodeType() : oagFpga::RtlGraph, oagFpga::OccGraph, oagFpga::ModGraph, oagFpga::AiModGraph
getNonInverted() : oagFpga::AiModGraph
getNull() : oagFpga::RtlGraph, oagFpga::OccGraph, oagFpga::ModGraph, oagFpga::AiModGraph
getNumOutputBits() : oagFpga::RtlGraph, oagFpga::ModGraph
getOutputBit() : oagFpga::RtlGraph
getOutputs() : oagFpga::OccGraph, oagFpga::ModGraph, oagFpga::AiModGraph
getParameterizedModuleName() : oagFpga::VerilogSynthesis
getPrimaryBBID() : oagFpga::RtlGraph, oagFpga::ModGraph
getSeq() : oagFpga::MapperUtils
getSequentialData() : oagFpga::AiModGraph
getSerializedSize() : oagFpga::Manager
getStates() : oagFpga::OccGraph
getTerminalDriver() : oagFpga::RtlGraph, oagFpga::OccGraph, oagFpga::ModGraph, oagFpga::AiModGraph
getTransitiveFanin() : oagFpga::RtlGraph, oagFpga::OccGraph, oagFpga::ModGraph, oagFpga::AiModGraph
getTransitiveFanin_recursive() : oagFpga::RtlGraph
getTransitiveFanout() : oagFpga::RtlGraph, oagFpga::OccGraph, oagFpga::ModGraph, oagFpga::AiModGraph
getTransitiveFanout_recursive() : oagFpga::RtlGraph
getUserData() : oagFpga::AiModGraph
getVector() : oagFunc::SimOcc, oagFpga::SimMod
greaterThan() : oagFpga::Synthesis
greaterThanEqual() : oagFpga::Synthesis

- h -

hasCombinationalCycle() : oagFpga::RtlGraph, oagFpga::ModGraph, oagFpga::AiModGraph
hasCombinationalCycle_recursive() : oagFpga::RtlGraph
hasFanout() : oagFpga::RtlGraph, oagFpga::OccGraph, oagFpga::ModGraph, oagFpga::AiModGraph
hasManager() : oagFpga::Manager

- i -

identifyControls() : oagFpga::MapperUtils
implementAll() : oagFpga::FpgaMapper
implementNode() : oagFpga::FpgaMapper
implementSeqNode() : oagFpga::FpgaMapper
incrementExternalReferences() : oagFpga::AiModGraph
initializeIncremental() : oagFunc::SimOcc, oagFpga::SimMod
initializeSimulation() : oagFpga::FpgaMapper
instantiateModule() : oagFpga::Synthesis
Instantiation() : oagFpga::VerilogDesign::Instantiation
isAnd() : oagFpga::AiModGraph
isAsynchronousSignal() : oagFpga::VerilogSynthesis
isConstantExpression() : oagFpga::VerilogSynthesis
isFunctional() : oagFpga::RtlGraph, oagFpga::ModGraph
isInverted() : oagFpga::AiModGraph
isNull() : oagFpga::RtlGraph, oagFpga::OccGraph, oagFpga::ModGraph, oagFpga::AiModGraph
isSequential() : oagFpga::RtlGraph, oagFpga::OccGraph, oagFpga::ModGraph, oagFpga::AiModGraph
isStructural() : oagFpga::Manager
isTerminal() : oagFpga::RtlGraph, oagFpga::OccGraph, oagFpga::ModGraph, oagFpga::AiModGraph
isVisited() : oagFpga::RtlGraph

- l -

latch() : oagFpga::Synthesis, oagFpga::ModuleCompiler
leftShift() : oagFpga::Synthesis
lessThan() : oagFpga::Synthesis, oagFpga::ModuleCompiler
lessThanEqual() : oagFpga::Synthesis
logicAnd() : oagFpga::Synthesis
logicNot() : oagFpga::Synthesis
logicOr() : oagFpga::Synthesis
LvalRef() : oagFpga::VerilogSynthesis::LvalRef

- m -

Manager() : oagFpga::Manager, oagFpga::RtlGraph
MapperUtils() : oagFpga::MapperUtils, oagFpga::Synthesis
markVisited() : oagFpga::RtlGraph
mergeEquivalentNets() : oagFpga::MapperUtils
ModRef() : oagFpga::ModRef
Module() : oagFpga::VerilogDesign::Module
multiBitConstant() : oagFpga::Synthesis, oagFpga::ModuleCompiler
MultiRef() : oagFpga::MultiRef
mux() : oagFpga::Synthesis, oagFpga::ModuleCompiler

- n -

nandOf() : oagFpga::Synthesis
newAnd() : oagFpga::AiModGraph
newNode() : oagFpga::RtlGraph
newSequential() : oagFpga::AiModGraph
newTerminal() : oagFpga::RtlGraph, oagFpga::AiModGraph
newTraversalID() : oagFpga::RtlGraph
nextCycle() : oagFunc::SimOcc, oagFpga::SimMod
norOf() : oagFpga::Synthesis
notEqualTo() : oagFpga::Synthesis
notOf() : oagFpga::Synthesis, oagFpga::ModuleCompiler, oagFpga::AiModGraph

- o -

Observer() : oagFpga::Observer
OccRef() : oagFpga::OccRef
onFirstOpen() : oagFpga::Observer
onPostSave() : oagFpga::Observer
onPreSave() : oagFpga::Observer
onPurge() : oagFpga::Observer
operator!=() : oagFpga::OccRef, oagFpga::ModRef, oagFpga::AiModRef
operator<() : oagFpga::OccRef, oagFpga::ModRef, oagFpga::AiModRef
operator=() : oagFpga::MultiRef
operator==() : oagFpga::OccRef, oagFpga::MultiRef, oagFpga::ModRef, oagFpga::AiModRef
orOf() : oagFpga::Synthesis, oagFpga::ModuleCompiler

- p -

PortConnection() : oagFpga::VerilogDesign::PortConnection
prepareNetToAiConnection() : oagFpga::Manager, oagFpga::AiModGraph
prepareNetToBBConnection() : oagFpga::ModGraph, oagFpga::Manager
Primary() : oagFpga::VerilogDesign::Primary
print() : oagFpga::RtlGraph, oagFpga::OccRef, oagFpga::ModRef, oagFpga::Manager, oagFpga::AiModRef, oagFpga::AiModGraph
printBitNetName() : oagFpga::VerilogSynthesis
printGateUsage() : oagFpga::MapperUtils
printName() : oagFpga::OccRef, oagFpga::ModRef, oagFpga::AiModRef
ProceduralState() : oagFpga::VerilogSynthesis::ProceduralState

- r -

randomVector() : oagFunc::SimOcc, oagFpga::SimMod
reductionAnd() : oagFpga::Synthesis, oagFpga::ModuleCompiler
reductionNand() : oagFpga::Synthesis
reductionNor() : oagFpga::Synthesis
reductionOr() : oagFpga::Synthesis, oagFpga::ModuleCompiler
reductionXnor() : oagFpga::Synthesis
reductionXor() : oagFpga::Synthesis, oagFpga::ModuleCompiler
removeAsyncResetsFromLogic() : oagFpga::MapperUtils
removeDanglingNets() : oagFpga::MapperUtils
removeEquivalences() : oagFpga::AiModGraph
removeFromFanout() : oagFpga::RtlGraph
removeNetToAiConnection() : oagFpga::Manager, oagFpga::AiModGraph
removeNetToBBConnection() : oagFpga::ModGraph
resubstitute() : oagFpga::AiModGraph
RtlGraph() : oagFpga::RtlGraph, oagFpga::RtlNode
RtlNode() : oagFpga::RtlNode
RtlSeqNodeInfo() : oagFpga::RtlNode::RtlSeqNodeInfo
runFull() : oagFunc::SimOcc, oagFpga::SimMod
runIncremental() : oagFunc::SimOcc, oagFpga::SimMod
runOne() : oagFpga::SimMod

- s -

scalarNet2Ai() : oagFpga::ModuleCompiler
seq() : oagFpga::Synthesis, oagFpga::ModuleCompiler
serialize() : oagFpga::Manager
setAndLeft() : oagFpga::AiModGraph
setAndRight() : oagFpga::AiModGraph
setAreaCosts() : oagFpga::FpgaMapper
setDelayCosts() : oagFpga::FpgaMapper
setEquivalent() : oagFpga::AiModGraph
setExternalTerminalConnection() : oagFpga::RtlGraph
setLibrary() : oagFpga::Synthesis
setLut() : oagFpga::MapperUtils
setNetToAiConnection() : oagFpga::Manager, oagFpga::AiModGraph
setNetToBBConnection() : oagFpga::ModGraph, oagFpga::Manager
setNextState() : oagFpga::AiModGraph
setOverwriteStructure() : oagFpga::Synthesis
setSeq() : oagFpga::MapperUtils
setTerminalDriver() : oagFpga::RtlGraph, oagFpga::ModGraph, oagFpga::AiModGraph
setUserData() : oagFpga::AiModGraph
setVector() : oagFunc::SimOcc, oagFpga::SimMod
setView() : oagFpga::Synthesis
SimMod() : oagFpga::SimMod, oagFpga::AiModGraph
SimOcc() : oagFunc::SimOcc
simulate() : oagFpga::FpgaMapper
Statement() : oagFpga::VerilogDesign::Statement
synthesize() : oagFpga::VerilogSynthesis
synthesizeBehavioral() : oagFpga::VerilogSynthesis
synthesizeBlock() : oagFpga::VerilogSynthesis
synthesizeBlockingassignment() : oagFpga::VerilogSynthesis
synthesizeCase() : oagFpga::VerilogSynthesis
synthesizeCaseEasy() : oagFpga::VerilogSynthesis
synthesizeIf() : oagFpga::VerilogSynthesis
synthesizeModule() : oagFpga::VerilogSynthesis
synthesizeModuleAssigns() : oagFpga::VerilogSynthesis
synthesizeModuleFunc() : oagFpga::VerilogSynthesis
synthesizeModuleInsts() : oagFpga::VerilogSynthesis
synthesizeModuleNets() : oagFpga::VerilogSynthesis
synthesizeModuleTerms() : oagFpga::VerilogSynthesis
synthesizeNonblockingassignment() : oagFpga::VerilogSynthesis

- t -

techmapArea() : oagFpga::FpgaMapper
techmapDelay() : oagFpga::FpgaMapper
testEquivalence() : oagFpga::AiModGraph
Trigger() : oagFpga::VerilogDesign::Trigger

- u -

unaryBusInputOutputOpt() : oagFpga::Synthesis, oagFpga::RtlGraph
unaryBusOpt() : oagFpga::Synthesis, oagFpga::RtlGraph
unaryOpt() : oagFpga::RtlGraph
unmarkVisited() : oagFpga::RtlGraph
unserialize() : oagFpga::Manager

- x -

xnorOf() : oagFpga::Synthesis
xorOf() : oagFpga::Synthesis, oagFpga::ModuleCompiler

- z -

zeroExpand() : oagFpga::Synthesis, oagFpga::ModuleCompiler

- ~ -

~AlwaysBlock() : oagFpga::VerilogDesign::AlwaysBlock
~Assignment() : oagFpga::VerilogDesign::Assignment
~Bundle() : oagFpga::VerilogDesign::Bundle
~Case() : oagFpga::VerilogDesign::Case
~Declaration() : oagFpga::VerilogDesign::Declaration
~Expression() : oagFpga::VerilogDesign::Expression
~Function() : oagFpga::VerilogDesign::Function
~Instantiation() : oagFpga::VerilogDesign::Instantiation
~Manager() : oagFpga::Manager
~Module() : oagFpga::VerilogDesign::Module
~Port() : oagFpga::VerilogDesign::Port
~PortConnection() : oagFpga::VerilogDesign::PortConnection
~Primary() : oagFpga::VerilogDesign::Primary
~RtlGraph() : oagFpga::RtlGraph
~RtlNode() : oagFpga::RtlNode
~Statement() : oagFpga::VerilogDesign::Statement
~Trigger() : oagFpga::VerilogDesign::Trigger
~VerilogDesign() : oagFpga::VerilogDesign

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