OA Gear Fpga: Class Members - Variables

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- a -

action : oagFpga::VerilogDesign::Case, oagFpga::VerilogDesign::AlwaysBlock, oagFpga::VerilogDesign::Function
aData : oagFpga::VerilogSynthesis::ProceduralState, oagFpga::RtlNode::RtlSeqNodeInfo
ai : oagFpga::Manager
aiRef : oagFpga::RtlNode
aLoad : oagFpga::VerilogSynthesis::ProceduralState, oagFpga::RtlNode::RtlSeqNodeInfo
alwaysBlocks : YYSTYPE, oagFpga::VerilogDesign::Module
arguments : oagFpga::VerilogDesign::Primary
assign : oagFpga::VerilogDesign::Statement
assignment : YYSTYPE
assignments : YYSTYPE, oagFpga::VerilogDesign::Module

- b -

bb : oagFpga::MultiRef
bbg : oagFpga::Manager
bbNodes : oagFpga::RtlGraph
begin_end : oagFpga::VerilogDesign::Statement
bits : YYSTYPE
BITS_PER_RAND : oagFunc::SimOcc, oagFpga::SimMod
bitWidth : oagFpga::VerilogDesign::Primary, oagFpga::Synthesis::ConstantValue
block : oagFpga::VerilogDesign::Statement
blockingAssignments : oagFpga::VerilogSynthesis::ProceduralState
bundle : YYSTYPE, oagFpga::VerilogDesign::Expression

- c -

cases : YYSTYPE, oagFpga::VerilogDesign::Statement
choice_n : oagFpga::FpgaMapper
choice_p : oagFpga::FpgaMapper
clock : oagFpga::RtlNode::RtlSeqNodeInfo
condition : oagFpga::VerilogSynthesis::ConditionalLvalRef, oagFpga::VerilogDesign::Statement
conditionalLval : oagFpga::VerilogSynthesis::LvalRef
conditions : oagFpga::VerilogDesign::Case
connections : oagFpga::VerilogDesign::Instantiation
CONSTANT0_BBREF : oagFpga::RtlGraph
CONSTANT1_BBREF : oagFpga::RtlGraph
constantZeroEntry : oagFpga::FpgaMapper
cost_n : oagFpga::FpgaMapper
cost_p : oagFpga::FpgaMapper
currentLibrary : oagFpga::Synthesis
currentManager : oagFpga::Synthesis, oagFpga::ModuleCompiler
currentModule : oagFpga::Synthesis
currentParams : oagFpga::VerilogSynthesis
currentTraversalID : oagFpga::RtlGraph
currentView : oagFpga::Synthesis
currentVmodule : oagFpga::VerilogSynthesis
curTrigger : oagFpga::VerilogSynthesis::ProceduralState
cut_n : oagFpga::FpgaMapper
cut_p : oagFpga::FpgaMapper
cutsPerNode : oagFpga::FpgaMapper

- d -

D : oagFpga::RtlNode::RtlSeqNodeInfo
data : oagFunc::SimOcc
dataBBNodes : oagFpga::RtlGraph
declaration : YYSTYPE
declarations : YYSTYPE, oagFpga::VerilogDesign::Statement, oagFpga::VerilogDesign::Function, oagFpga::VerilogDesign::Module
decls : YYSTYPE
dependencies : oagFpga::VerilogSynthesis::ProceduralState
design : oagFpga::VerilogDesign::Module, oagFunc::SimOcc, oagFpga::SimMod, oagFpga::Manager

- e -

exhaustiveInputVectors : oagFpga::FpgaMapper
expression : YYSTYPE
expressions : YYSTYPE
externalName : oagFpga::VerilogDesign::Port
externalTerminalConnection : oagFpga::RtlNode

- f -

fanin : oagFpga::RtlNode
fanout : oagFpga::RtlNode
finishedModules : oagFpga::VerilogSynthesis
functionAssignments : oagFpga::VerilogSynthesis::ProceduralState
functionLvalBit : oagFpga::VerilogSynthesis::LvalRef
functionLvalName : oagFpga::VerilogSynthesis::LvalRef
functions : YYSTYPE, oagFpga::VerilogDesign::Module
funcType : oagFpga::RtlNode
funcTypeName : oagFpga::RtlNode

- g -

gateCount : oagFpga::FpgaMapper

- i -

ifc : oagFpga::VerilogDesign::Statement
ifFalse : oagFpga::VerilogDesign::Statement
ifTrue : oagFpga::VerilogDesign::Statement
in : oagFpga::RtlNode::RtlMuxNodeInfo
initialBlocks : YYSTYPE, oagFpga::VerilogDesign::Module
instantiation : YYSTYPE
instantiations : YYSTYPE, oagFpga::VerilogDesign::Module
internalName : oagFpga::VerilogDesign::Port
intValue : oagFpga::VerilogDesign::Primary, oagFpga::Synthesis::ConstantValue
isDefault : oagFpga::VerilogDesign::Case
isFunction : oagFpga::VerilogSynthesis::ProceduralState
isRegister : oagFpga::VerilogSynthesis::ProceduralState

- l -

lastManagerDesign : oagFpga::Manager
lastManagerObject : oagFpga::Manager
leafLibs : oagFpga::Synthesis
leafViews : oagFpga::Synthesis
lower : oagFpga::Synthesis::Bounds
lutArea : oagFpga::MapperUtils
lutDelay : oagFpga::MapperUtils
lutGate : oagFpga::MapperUtils
lutInputs : oagFpga::MapperUtils
lutOutput : oagFpga::MapperUtils
lval : oagFpga::VerilogSynthesis::ConditionalLvalRef, oagFpga::VerilogDesign::Statement, oagFpga::VerilogDesign::Assignment

- m -

mapped : oagFpga::FpgaMapper
mapUtils : oagFpga::FpgaMapper
members : oagFpga::VerilogDesign::Bundle
module : YYSTYPE, oagFpga::ModRef, oagFpga::AiModRef
modules : oagFpga::VerilogDesign
muxInfo : oagFpga::RtlNode

- n -

name : oagFpga::VerilogDesign::Primary, oagFpga::VerilogDesign::PortConnection, oagFpga::VerilogDesign::Instantiation, oagFpga::VerilogDesign::Statement, oagFpga::VerilogDesign::Function, oagFpga::VerilogDesign::Declaration, oagFpga::VerilogDesign::Module
NAME_LENGTH_LIMIT : oagFpga::Synthesis
nameSpace : oagFpga::Synthesis
negAsyncResets : oagFpga::MapperUtils
negative : YYSTYPE, oagFpga::VerilogDesign::Primary
negClocks : oagFpga::MapperUtils
negTriggers : oagFpga::VerilogSynthesis::ProceduralState
net : oagFpga::VerilogDesign::Trigger, oagFpga::MultiRef
nonblockingAssignments : oagFpga::VerilogSynthesis::ProceduralState
nonClockTriggers : oagFpga::VerilogSynthesis::ProceduralState
normalTriggers : oagFpga::VerilogSynthesis::ProceduralState
notEntry : oagFpga::FpgaMapper
NULL_BBREF : oagFpga::RtlGraph
number : YYSTYPE, oagFpga::VerilogDesign::Primary
numOutputBits : oagFpga::RtlNode

- o -

occurrence : oagFpga::OccRef
op1 : oagFpga::VerilogDesign::Expression, oagFpga::RtlNode::RtlOptNodeInfo
op2 : oagFpga::VerilogDesign::Expression, oagFpga::RtlNode::RtlOptNodeInfo
op3 : oagFpga::VerilogDesign::Expression, oagFpga::RtlNode::RtlOptNodeInfo
optInfo : oagFpga::RtlNode
optType : oagFpga::RtlNode
optTypeName : oagFpga::RtlNode
overwriteStructure : oagFpga::Synthesis

- p -

parameterOverrides : YYSTYPE, oagFpga::VerilogDesign::Module
parameters : oagFpga::VerilogDesign::Instantiation, oagFpga::VerilogDesign::Module
portConnection : YYSTYPE
portConnections : YYSTYPE
ports : YYSTYPE, oagFpga::VerilogDesign::Module
posAsyncResets : oagFpga::MapperUtils
posClocks : oagFpga::MapperUtils
position : oagFpga::VerilogDesign::PortConnection, oagFpga::VerilogDesign::Port
posTriggers : oagFpga::VerilogSynthesis::ProceduralState
primaries : YYSTYPE
primary : YYSTYPE, oagFpga::VerilogDesign::Expression
primitive : oagFpga::VerilogDesign::Instantiation
pStateType : oagFpga::VerilogSynthesis::ProceduralState

- r -

range : oagFpga::VerilogDesign::Primary
ref : oagFpga::OccRef, oagFpga::ModRef, oagFpga::AiModRef
replication : oagFpga::VerilogDesign::Bundle
rval : oagFpga::VerilogDesign::Statement

- s -

sel : oagFpga::RtlNode::RtlMuxNodeInfo
self : oagFpga::RtlNode
seqArea : oagFpga::MapperUtils
seqClock : oagFpga::MapperUtils
seqClockTrigger : oagFpga::MapperUtils
seqCount : oagFpga::FpgaMapper
seqDelay : oagFpga::MapperUtils
seqGate : oagFpga::MapperUtils
seqInfo : oagFpga::RtlNode
seqInput : oagFpga::MapperUtils
seqOutput : oagFpga::MapperUtils
seqPreset : oagFpga::MapperUtils
seqPresetTrigger : oagFpga::MapperUtils
seqReset : oagFpga::MapperUtils
seqResetTrigger : oagFpga::MapperUtils
seqType : oagFpga::RtlNode
seqTypeName : oagFpga::RtlNode
SIM_USER_DATA_INDEX : oagFpga::SimMod
start : oagFpga::VerilogSynthesis::FunctionVariableAssignment, oagFpga::VerilogDesign::Primary, oagFpga::VerilogDesign::Function, oagFpga::VerilogDesign::Declaration
start2D : oagFpga::VerilogDesign::Declaration
statement : YYSTYPE
statements : YYSTYPE
stop : oagFpga::VerilogSynthesis::FunctionVariableAssignment, oagFpga::VerilogDesign::Primary, oagFpga::VerilogDesign::Function, oagFpga::VerilogDesign::Declaration
stop2D : oagFpga::VerilogDesign::Declaration
str : YYSTYPE

- t -

toBeSimulated : oagFunc::SimOcc, oagFpga::SimMod
totalArea : oagFpga::FpgaMapper
totalDelay : oagFpga::FpgaMapper
traversalID : oagFpga::RtlNode
trigger : YYSTYPE
triggers : YYSTYPE, oagFpga::VerilogDesign::AlwaysBlock
twoDimRegisters : oagFpga::VerilogSynthesis
type : oagFpga::VerilogSynthesis::LvalRef, oagFpga::VerilogDesign::Primary, oagFpga::VerilogDesign::Expression, oagFpga::VerilogDesign::Instantiation, oagFpga::VerilogDesign::Statement, oagFpga::VerilogDesign::Trigger, oagFpga::VerilogDesign::Declaration, oagFpga::MultiRef

- u -

unconditionalLval : oagFpga::VerilogSynthesis::LvalRef
upper : oagFpga::Synthesis::Bounds

- v -

value : YYSTYPE, oagFpga::VerilogDesign::PortConnection, oagFpga::VerilogDesign::Assignment, oagFpga::VerilogDesign::Declaration

- x -

xMask : oagFpga::VerilogDesign::Primary
xmask : YYSTYPE

- z -

zmask : YYSTYPE
zMask : oagFpga::VerilogDesign::Primary

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